Dynamic frequency and voltage control for a multiple clock domain microarchitecture

Semeraro, Greg; Albonesi, David H.; Dropsho, Steven; Magklis, Grigorios; Dwarkadas, Sandhya; Scott, Michael L.

doi:10.1109/micro.2002.1176263

Cited by 92 publications

(179 citation statements)

References 19 publications

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“…Multiple clock domains may be required either due to different external frequencies, or the integration of modules that were designed to operate on different frequencies, or to facilitate clock gating and partitioning of large and fast clock trees. In addition, frequency and voltage may also be changed dynamically in Dynamic Voltage and Frequency Scaling (DVFS) systems [1]- [3], mainly to reduce power consumption.…”

Section: Introductionmentioning

confidence: 99%

Fast Universal Synchronizers

Dobkin

Ginosar

2009

Lecture Notes in Computer Science

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Abstract.Synchronization circuits are essential in multi-clock-domain systems-on-chip. The most well-known synchronizer consists of two sequentially connected flip-flops that should eliminate the propagation of metastability into the receiver clock domain. We first clarify how such a simple "two-flop" synchronizer can be used in the system, and analyze its performance, showing that the data cycle may be as long as 12 clock cycles. Novel faster synchronizers are described next and their use and improved performance are explained. The fast synchronizer enable shorter data cycles, measuring only 2 to 4 clock cycles. Synchronizer performance is also analyzed when the two communicating clock domains are separated by long interconnect, incurring additional latencies.

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Section: Introductionmentioning

confidence: 99%

Fast Universal Synchronizers

Dobkin

Ginosar

2009

Lecture Notes in Computer Science

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“…Second, we propose a new DVS policy that adapts the core and L2 cache speeds in a way that avoids these inefficiencies, taking into account domain interactions. Third, we show positive gains of our policy against a well-known online DVS policy [3].…”

Section: Introductionmentioning

confidence: 59%

“…The performance penalty is less than 5% and 6.5%, respectively. Compared to a well-known online MCD DVS policy [3], we show an additional improvement in the energy-delay product of 3.5% and 7%, on average (up to 13%), with minimal performance degradation. Our policy requires no additional hardware beyond what is already available in MCD design.…”

Section: Introductionmentioning

confidence: 74%

“…In general, application phases correspond to loops, and a new phase is entered when control branches to a different code section. Since we are interested in the performance and energy of the CPU core and L2 cache, we characterize each code segment in a program using performance monitors that relate to the activity in each of these domains [3]. Figure 2 shows the variations in two performance counters (cycle-per-instruction and number of L2 accesses) as examples of monitors that can be used to represent a program behavior.…”

Section: Application and MCD Chip Modelsmentioning

confidence: 99%

“…When queue length increases, the domain speed is increased; when queue length decreases, the speed is decreased. In general, policies in the literature [3] [4][5] [6] focus on each domain in isolation without considering possible inter-domain effects when varying speed.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Integrated CPU Cache Power Management in Multiple Clock Domain Processors

AbouGhazaleh

Childers

Mossé

et al.

High Performance Embedded Architectures and Compilers

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Abstract. Multiple clock domain (MCD) chip design addresses the problem of increasing clock skew in different chip units. Importantly, MCD design offers an opportunity for fine grain power/energy management of the components in each clock domain with dynamic voltage scaling (DVS). In this paper, we propose and evaluate a novel integrated DVS approach to synergistically manage the energy of chip components in different clock domains. We focus on embedded processors where core and L2 cache domains are the major energy consumers. We propose a policy that adapts clock speed and voltage in both domains based on each domain's workload and the workload experienced by the other domain. In our approach, the DVS policy detects and accounts for the effect of inter-domain interactions. Based on the interaction between the two domains, we select an appropriate clock speed and voltage that optimizes the energy of the entire chip. For the Mibench benchmarks, our policy achieves an average improvement over nopower-management of 15.5% in energy-delay product and 19% in energy savings. In comparison to a traditional DVS policy for MCD design that manages domains independently, our policy achieves an 3.5% average improvement in energy-delay and 4% less energy, with a negligible 1% decrease in performance. We also show that an integrated DVS policy for MCD design with two domains is more energy efficient for simple embedded processors than high-end ones.

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Energy‐based tuning of metaheuristics for molecular docking on multi‐GPUs

Pérez-Serrano

Imbernón

Cecilia

et al. 2018

Concurrency and Computation

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Summary Virtual Screening (VS) methods simulate molecular interactions in silico to look for the best chemical compound that interacts with a given molecular target. VS is becoming increasingly popular to accelerate the drug discovery process and constitute hard optimization problems with a huge computational cost. To deal with these two challenges, we have created METADOCK, an application that (1) enables a wide range of metaheuristics through a parametrized schema and (2) promotes the use of a multi‐GPU environment within a heterogeneous cluster. Metaheuristics provide approximate solutions in a reasonable time frame, but, given the stochastic nature of real‐life procedures, the energy budget goes hand in hand with acceleration to validate the proposed solution. This paper evaluates energy trade‐offs and correlations with performance for a set of metaheuristics derived from METADOCK. We establish a solid inference from minimal power to maximal performance in GPUs, and from there, to optimal energy consumption. This way, ideal heuristics can be chosen according not only to best accuracy and performance but also to energy requirements. Our study starts with a preselection of parameterized metaheuristic functions, building blocks where we will find optimal patterns from power criteria while preserving parallelism through a GPU execution. We then establish a methodology to figure out the best instances of the parameterized kernels based on energy patterns obtained, which are analyzed from different viewpoints, ie, performance, average power, and total energy consumed. We also compare the best workload distributions for optimal performance and power efficiency among Pascal and Maxwell GPUs on popular Titan models. Our experimental results demonstrate that the most power efficient GPU can be overloaded in order to reduce the total amount of energy required by as much as 20%, finding unique scenarios where Maxwell does it better in execution time, but with Pascal always ahead in performance per watt, reaching peaks of up to 40%.

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Dynamic frequency and voltage control for a multiple clock domain microarchitecture

Abstract: We describe the design, analysis, and performance of an on-line

Cited by 92 publications

References 19 publications

Fast Universal Synchronizers

Fast Universal Synchronizers

Integrated CPU Cache Power Management in Multiple Clock Domain Processors

Energy‐based tuning of metaheuristics for molecular docking on multi‐GPUs

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