Dynamic management of TurboMode in modern multi-core chips

Abstract

Dynamic overclocking of CPUs, or TurboMode, is a feature recently introduced on all x86 multi-core chips. It leverages thermal and power headroom from idle execution resources to overclock active cores to increase performance. TurboMode can accelerate CPU-bound applications at the cost of additional power consumption. Nevertheless, naive use of TurboMode can significantly increase power consumption without increasing performance. Thus far, there is no strategy for managing TurboMode to optimize its use across all workloads and efficiency metrics.This paper analyzes the impact of TurboMode on a wide range of efficiency metrics (performance, power, cost, and combined metrics such as QPS/W and ED 2 ) for representative server workloads on various hardware configurations. We determine that TurboMode is generally beneficial for performance (up to +24%), cost efficiency (QPS/$ up to +8%), energy-delay product (ED, up to +47%), and energy-delay-squared product (ED 2 , up to +68%). However, TurboMode is inefficient for workloads that exhibit interference for shared resources. We use this information to build and validate a model that predicts the optimal TurboMode setting for each efficiency metric. We then implement autoturbo, a background daemon that dynamically manages TurboMode in real time without any hardware changes. We demonstrate that autoturbo improves QPS/$, ED, and ED 2 by 8%, 47%, and 68% respectively over not using TurboMode. At the same time, autoturbo virtually eliminates all the large drops in those same metrics (-12%, -25%, -25% for QPS/$, ED, and ED 2 ) that occur when TurboMode is used naively (always on).

Rubik

“…However, recent work has shown that these schemes are unsuitable for latencycritical applications since they focus on long-term performance and severely hurt tail latency [24,33,34,39].…”

“…HW-T and HW-TPW are hardware-controlled schemes that perform coordinated per-core DVFS: HW-T sets frequencies to maximize aggregate system throughput (IPC) while staying below TDP; HW-TPW maximizes aggregate throughput per watt. These schemes adapt every 100 µs, and represent hardware-controlled DVFS schemes typical of modern chips (e.g., Turbo Boost [34,46]). All schemes use a partitioned memory system.…”

Peak efficiency aware scheduling for highly energy proportional servers

“…Energy proportional computing: Energy proportional computing have been a major area of research [1], [5], [6], [9], [15], [18], [35]- [37]. In addition, measurements, metrics and trends of energy proportionality have all been well studied [19], [21], [22], [35], [38].…”

“…Active low power modes, on the other hand, remains effective even with multi-core scaling [8], [18]. Commercially available active low power modes includes DVFS [5], where the processor's voltage and frequency are scaled down as the server's workload decreases. While this work does not explore component and server-level energy proportionality techniques, it does rely on high energy proportional servers.…”

“…Energy proportional innovations have targeted improvement at the component-level [2]- [5], server-level [6]- [9], and cluster-level [10]- [15]. Component-level innovations typically leverage techniques such as dynamic voltage frequency scaling (DVFS) and power gating.…”