Dynamic objects: Supporting fast and easy run-time reconfiguration in FPGAs

Dondo, Julio; Barba, Jesús; Rincón, Fernando; Moya, Francisco; López, Juan Carlos

doi:10.1016/j.sysarc.2012.09.001

Cited by 19 publications

(10 citation statements)

References 20 publications

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“…Authors presented dynamic reconfiguration of the FPGA depended on most of hardware virtualization schemes. The idea is decomposing the physical FPGA into several reconfigurable regions by using dynamic partial reconfiguration (DPR) [10,11]. FPGA resources sharing is a requirement and promising technique to reuse resources for different configuration circuits.…”

Section: Overlays For High Productivity and Portabilitymentioning

confidence: 99%

A SLM-based overlay architecture for fine-grained virtual FPGA

Myint

Amagasaki

Zhao

et al. 2019

IEICE Electron. Express

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FPGA overlay technologies have been introduced to provide inter-FPGA bitstream compatibility by implementing virtual FPGA (vFPGA) layers on physical devices. Conventional LUT-based fine-grained vFPGAs have very large resource overheads. In this paper, we propose a fine-grained vFPGA overlay architecture that employs our previously proposed scalable logic module (SLM) as a logic cell. SLMs can cover most frequently used logics with far fewer hardware resources than LUTs. Evaluation results show that a 7-input SLM-based vFPGA can reduce LUT and flip-flop resource usage by up to 32% and 35% on an Artix-7 FPGA, 30% and 35% on a Kintex-7 FPGA, and 30% and 35% on a Kintex UltraScale+ FPGA respectively, as compared to a LUT-based vFPGA of the same input size.

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Section: Overlays For High Productivity and Portabilitymentioning

confidence: 99%

A SLM-based overlay architecture for fine-grained virtual FPGA

Myint

Amagasaki

Zhao

et al. 2019

IEICE Electron. Express

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“…The work proposed here resorts to the infrastructure for dynamic reconfiguration management for Xilinx platforms developed by Dondo et al [26] in order to make the Scone hardware platform an entity that scales well through the addition of new processing cores when it is required.…”

Section: Dynamic Reconfiguration Managementmentioning

confidence: 99%

“…Following, a brief description of the process and supporting architecture devised in [26] is provided to the reader. The goal is to offer a global solution to the main challenges that make it possible to take full advantage of partial and dynamic reconfiguration.…”

Section: Dynamic Reconfiguration Managementmentioning

confidence: 99%

FPGA acceleration of semantic tree reasoning algorithms

Barba

Santofimia

Dondo

et al. 2015

Journal of Systems Architecture

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“…Dynamically and partially reconfigurable architectures rely on reconfiguration engines that allow hardware reusability within the same chip [1] [2]. These reconfiguration engines manage the process of modifying the device configuration memory by sending commands and configuration information through a reconfiguration port.…”

Section: A Dynamic and Partial Reconfigurationmentioning

confidence: 99%

Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration

Rodríguez

Valverde

Torre

et al. 2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-Ever demanding systems with restricted resources face increasingly complex applications. Additionally, changeable environments modify working conditions over time. Therefore, a dynamic resource management is required in order to provide adaptation capabilities. By using ARTICo 3 , a bus-based architecture with reconfigurable slots, this adaptation is accomplished in three different but dependent areas: Consumption, Confidentiality and fault tolerance, and Computation. The proposed resource management strategies rely on an architecture and a model of computation that make execution configuration to be application-independent, but context-aware, since a CUDA-like execution model is used. The inherent and explicit application-level parallelism of multithreaded CUDA kernels is used to generate hardware accelerators that act as thread blocks. Despite other modes of operation provided by the ARTICo 3 architecture, like module redundancy or dual-rail operation to mitigate Side-Channel Attacks, these thread blocks are dynamically managed and their execution is scheduled using a multiobjective optimization algorithm.

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Dynamic objects: Supporting fast and easy run-time reconfiguration in FPGAs

Cited by 19 publications

References 20 publications

A SLM-based overlay architecture for fine-grained virtual FPGA

A SLM-based overlay architecture for fine-grained virtual FPGA

FPGA acceleration of semantic tree reasoning algorithms

Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration

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