Dynamic parallelization of single-threaded binary programs using speculative slicing

Wang, Cheng; Wu, Youfeng; Borin, Edson; Hu, Shiliang; Liu, Wei; Sager, D.J.; Ngai, Tin-Fook; Fang, Juan

doi:10.1145/1542275.1542302

Cited by 29 publications

(17 citation statements)

References 24 publications

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“…Binary rewriter parallelization systems [35,64,68] take as input a sequential binary executable program and produce as output a parallel binary executable. Dynamic code generating binary parallelization systems [13,27] assume the existence of TLS hardware and apply the same control flow graph analyses used by conventional TLS compilers to sequential binary programs not originally compiled for TLS.…”

Section: Binary Parallelizationmentioning

confidence: 99%

Asc

Waterland

Angelino

Adams

et al. 2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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We present an architecture designed to transparently and automatically scale the performance of sequential programs as a function of the hardware resources available. The architecture is predicated on a model of computation that views program execution as a walk through the enormous state space composed of the memory and registers of a singlethreaded processor. Each instruction execution in this model moves the system from its current point in state space to a deterministic subsequent point. We can parallelize such execution by predictively partitioning the complete path and speculatively executing each partition in parallel. Accurately partitioning the path is a challenging prediction problem. We have implemented our system using a functional simulator that emulates the x86 instruction set, including a collection of state predictors and a mechanism for speculatively executing threads that explore potential states along the execution path. While the overhead of our simulation makes it impractical to measure speedup relative to native x86 execution, experiments on three benchmarks show scalability of up to a factor of 256 on a 1024 core machine when executing unmodified sequential programs.

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Section: Binary Parallelizationmentioning

confidence: 99%

Asc

Waterland

Angelino

Adams

et al. 2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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“…Dynamic parallelization is another approach to speedup applications in a multicore environment [17,2,16,6]. These approaches identify parallel code within an application and create micro threads on independent cores to run that parallel code.…”

Section: Related Workmentioning

confidence: 99%

“…These approaches identify parallel code within an application and create micro threads on independent cores to run that parallel code. Micro threads are speculative-if data dependencies are violated [2,16,6] or trace early exits are taken [17], the system must rollback somehow. In contrast, our system focuses on optimizing sequential code and executes software compensation routines instead of performing complete rollbacks.…”

Section: Related Workmentioning

confidence: 99%

A framework to accelerate sequential programs on homogeneous multicores

Fletcher

Harding

Khan

et al. 2013

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

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This paper presents a light-weight dynamic optimization framework for homogeneous multicores. A dynamic optimizer speculates that certain program paths are hot at runtime, optimizes those paths as if they were a single basic block, and provides the application a way to fetch the optimized code. Our approach offloads dynamic optimization to a Partner core and strives to minimize dedicated hardware overhead. Cheaply implementing dynamic optimization with a Partner core is possible because (1) dynamic optimizers are naturally loosely-coupled and (2) hot paths are repetitive by nature. These two properties make the optimization process time-insensitive and require minimal dedicated hardware to implement.We show how our system enables different SPEC06int applications to execute on average 52 % of their dynamic instructions from within traces. We then show that our system is resilient to the latency of the optimization process, to the placement of the Partner core on the chip, and to the Partner core clock frequency. Given the insight that quality of results is resilient to Partner core frequency scaling, we present a 2-core design point that-without additional compiler optimizations-improves power dissipation by 7 % compared to a 1-core baseline and only degrades performance by 2 %. With the mechanisms we present, our results are attainable with < 50 Bytes of dedicated hardware.

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“…Existing DBP technologies are generally divided into two main categories: parallelizing the raw dynamic instruction stream (DIS) [3,4,5] and parallelizing the dynamically-generated CFG [6,7,8,9,10].…”

Section: Problems Of State-of-the-art Dbpmentioning

confidence: 99%

“…DIS-based DBP techniques [3,4,5] usually rely on some centralized memory disambiguation unit to compare the address of each load or store instruction. Similarly, CFG-based DBP techniques [6,7,9] require special hardware support such as transactional memory to automatically detect violations of memory reference order. Tracy can insert all non-alias condition tests directly into the trace and treat them as normal instructions, which, however, greatly restricts the number of memory reference groups that can be tested in order to maintain reasonable monitoring overhead.…”

Section: Memory Disambiguationmentioning

confidence: 99%

Trace-Based Dynamic Binary Parallelization

Yang¹

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With the number of cores increasing rapidly but the performance per core increasing slowly at best, software must be parallelized in order to improve performance. Manual parallelization is often prohibitively time-consuming and error-prone (especially due to data races and memory-consistency complexities), and some portions of code may simply be too difficult to understand or refactor for parallelization. Most existing automatic parallelization techniques are performed statically at compile time and require source code to be analyzed, leaving a large fraction of software behind.In many cases, some or all of the source code and development tool chain is lost or, in the case of third-party software, was never available. Furthermore, modern applications are assembled and defined at run time, making use of shared libraries, virtual functions, plugins, dynamically-generated code, and other dynamic mechanisms, as well as multiple languages. All these aspects of separate compilation prevent the compiler from obtaining a holistic view of the program, leading to the risk of incompatible parallelization techniques, subtle data races, and resource over-subscription. All the above considerations motivate dynamic binary parallelization (DBP).This dissertation explores the novel idea of trace-based DBP, which provides a large instruction window without introducing spurious dependencies. We hypothesize that traces provide a generally good trade-off between code visibility and analysis accuracy for a wide variety of applications so as to achieve better parallel performance. Compared to the raw dynamic instruction stream (DIS), traces expose more distant parallelism opportunities because their average length is typically much larger than the size of the hardware instruction window. Compared to the complete control flow graph (CFG), traces only contain control and data dependencies on the execution path which is actually taken. More importantly, while DIS-based DBP typically only exploits fine-grained parallelism and CFG-based DBP typically only exploits coarse-grained parallelism, traces can be used as a unified representation of program execution to seamlessly incorporate the exploitation of both coarse-and fine-grained parallelism.We develop Tracy, an innovative DBP framework which monitors a program at run time and i Abstract ii dynamically identifies hot traces, parallelizes them, and caches them for later use so that the program can run in parallel every time a hot trace repeats. Our experimental results have demonstrated that for floating point benchmarks, Tracy can achieve an average speedup of 2.16x, 1.51x better than the speedup achieved by Core Fusion, one representative of DIS-based DBP techniques. Although the average speedup achieved by Tracy is only 1.04x better than the speedup achieved by CFG-based DBP, Tracy can speed up all floating point benchmarks while CFG-based DBP fails to parallelize three out of eight applications at all. The performance of Tracy is not always better than the performance of exist...

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Dynamic parallelization of single-threaded binary programs using speculative slicing

Cited by 29 publications

References 24 publications

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A framework to accelerate sequential programs on homogeneous multicores

Trace-Based Dynamic Binary Parallelization

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