2023
DOI: 10.1631/fitee.2200084
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Dynamic power-gating for leakage power reduction in FPGAs

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Cited by 3 publications
(1 citation statement)
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“…The approach involves load capacitance reduction, the utilization of dual threshold voltages, and minimizing clock jumps. Jahanirad, H. [ 19 ] proposed an energy-efficient architecture for static random access memory (SRAM)-based FPGAs. The architecture defines each module with two modes: active and sleep.…”
Section: Introductionmentioning
confidence: 99%
“…The approach involves load capacitance reduction, the utilization of dual threshold voltages, and minimizing clock jumps. Jahanirad, H. [ 19 ] proposed an energy-efficient architecture for static random access memory (SRAM)-based FPGAs. The architecture defines each module with two modes: active and sleep.…”
Section: Introductionmentioning
confidence: 99%