Dynamic power management for microprocessors: a case study

ACM Trans. Des. Autom. Electron. Syst.

2006

Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts indicate that architectures, compilers, and software can be optimized so as to reduce the switching power (also known as dynamic power) in microprocessors. This has lead to interest in using architecture and compiler optimization to reduce leakage power (also known as static power) in microprocessors. In this article, we investigate compileranalysis techniques that are related to reducing leakage power. The architecture model in our design is a system with an instruction set to support the control of power gating at the component level. Our compiler provides an analysis framework for utilizing instructions to reduce the leakage power. We present a framework for analyzing data flow for estimating the component activities at fixed points of programs whilst considering pipeline architectures. We also provide equations that can be used by the compiler to determine whether employing power-gating instructions in given program blocks will reduce the total energy requirements. As the duration of power gating on components when executing given program routines is related to the number and complexity of program branches, we propose a set of scheduling policies and evaluate their effectiveness. We performed experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumptions on Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing leakage power in microprocessors.

Section: Related Workmentioning

confidence: 99%

Compilers for leakage power reduction

ACM Trans. Des. Autom. Electron. Syst.

2006

“…Recently, new research directions in reducing power consumptions have begun to address the issues on the aspect of architecture designs and on software arrangements at instruction-level to help reduce power consumptions. [1,5,8,11,12,17,19,20]. In order to reduce the dynamic power, several research work have been proposed to reduce the dissipation.…”

Section: Introductionmentioning

confidence: 99%

“…In order to reduce the dynamic power, several research work have been proposed to reduce the dissipation. For example, software rearrangements to utilize the value locality of registers [5], the swapping of operands for booth multiplier [12], the scheduling of VLIW instructions to reduce the power consumption on the instruction bus [11], gating clock to reduce workloads [8,19,20], cache sub-banking mechanism [17], the utilization of instruction cache [1], etc.…”

Section: Introductionmentioning

confidence: 99%

A sink-n-hoist framework for leakage power reduction

Huang

Proceedings of the 5th ACM International Conference on Embedded Software

2005

Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture and compiler solutions to employ power-gating mechanisms to reduce leakage power. This approach is to have compilers perform data-flow analysis and insert instructions at programs to shut down and wake up components whenever appropriate for power reductions. While this approach has been shown to be effective in early studies, there are concerns for the amount of power-control instructions being added to programs with the increasing amount of components equipped with power-gating control in a SoC design platform. In this paper, we present a Sink-N-Hoist framework in the compiler solution to generate balanced scheduling of power-gating instructions. Our solution will attempt to merge power-gating instructions as one compound instruction. Therefore, it will reduce the amount of power-gating instructions issued. We perform experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumptions on Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further in reducing leakage power compared to previous methods.

“…Numerous studies in the literature on low-power design have proposed various techniques for synthesizing designs with reduced transitional activities. Recently, the prospect of combining architecture design and software arrangement at the instruction level has been addressed to help reduce power consumption [Bellas et al 2000;Chang and Pedram 1995;Horowitz et al 1994;Lee et al 2003;Su and Despain 1995;Tiwari et al 1998Tiwari et al , 1997 For example, several types of software rearrangement have been used to reduce the dynamic power, such as utilizing the value locality of registers [Chang and Pedram 1995], swapping operands for Booth multipliers [Lee et al 1997], scheduling VLIW instructions to reduce the power consumption on the instruction bus [Lee et al 2003], gating the clock to reduce workloads [Horowitz et al 1994;Tiwari et al 1998Tiwari et al , 1997, utilizing cache subbanking mechanisms [Su and Despain 1995], and an instruction cache for loops [Bellas et al 2000].…”

Section: Introductionmentioning

confidence: 99%

Compilation for compact power-gating controls

Huang

ACM Trans. Des. Autom. Electron. Syst.

2007

Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies due to the continuing size reductions and increasing speeds of transistors. Recent studies have attempted to reduce leakage power using integrated architecture and compiler power-gating mechanisms. This approach involves compilers inserting instructions into programs to shut down and wake up components, as appropriate. While early studies showed this approach to be effective, there are concerns about the large amount of power-control instructions being added to programs due to the increasing amount of components equipped with power-gating controls in SoC design platforms. In this article we present a sink-n-hoist framework for a compiler to generate balanced scheduling of power-gating instructions. Our solution attempts to merge several power-gating instructions into a single compound instruction, thereby reducing the amount of power-gating instructions issued. We performed experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumption using Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further reducing leakage power compared to previous methods.