Dynamic Power Management for Neuromorphic Many-Core Systems

Abstract

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing

“…The QPE logically combines 4 PEs and a NoC router, with connections to the PEs and the four neighbor QPEs. It is implemented in a globally-asynchronous-locally-synchronous (GALS) clocking scheme, allowing the PEs to operate in the dynamic voltage and frequency scaling (DVFS) scheme from [8] independent from each other and the NoC router logic. Additionally, the GALS approach also decouple the QPEs from each other to prevent the need for a chip top-level synchronous clock distribution network.…”

“…tbd are with the Faculty of Electrical and Computer Engineering, Technische Universität Dresden, Germany (e-mail: sebastian.hoeppner@tudresden. de) tbd are with the Advanced Processor Technologies Research Group, University of Manchester spiking activity computed on the cores [7], [8]. The Arm Cortex-M4 cores employed for SpiNNaker2 integrate a singleprecision floating point unit, thus extending the fixed-point arithmetic of the first generation SpiNNaker.…”

SpiNNaker: A Spiking Neural Network Architecture

“…Although it is desired to operate the PE at the MEP for maximum efficiency, this obviously does not result in significant processor performance scaling compared to SpiNNaker1. Performance enhancement is achieved by applying Dynamic Voltage and Frequency Scaling (DVFS) [106,107] to the PE. As shown in Figure 8.3 the PE core logic can be connected to one of two supply voltage rails.…”

“…As shown in Figure 8.3 the PE core logic can be connected to one of two supply voltage rails. This allows for energy-efficient operation at a low-performance level at 0.50 V and peak performance operation at a higher-performance level at 0.60 V. It has been shown [106,107] that under the dynamics of spiking neuromorphic applications, where peak processing power is only required in few simulation cycles, this technique significantly reduces the PE power consumption while still maintaining the temporal peak performance of the PE. The performance level transition is scheduled from a local power management controller at QPE level, based on the concept from [105].…”

“…PyNN,84,[103][104][105][106]110,113,114,118,119,122,126,130,138,171,183,185,204,207,219,222,250, 256 Python, 84, 85, 87, 89, 91, 97, 99, 103, 106, 119, 122, 171, 227 QPE, xxi, 266-268, 270, 279 Qualcomm, 263 quantum computer, 148 RAM, xxi, 8, 10, 14, 19, 25-27, 31, 34, 44, 46, 48, 49, 51, 147 Ramón y Cajal, 3 random initialisation, 259 random mutation, 256 random number generator, 272 rank-order encoding, 250, 254 Raspberry-Pi, 146, 147 RBM, xxi, 161, 162, 170, 189 read-modify-write operation, 39 unsupervised learning, 161, 170, 227, 229, 247, 249, 250 user, 44, 47, 48, 55, 74, 77, 78, 84, 89, 92, 103-105, 107, 108, 110, 112, 116-119, 139, 142, 143, 146, 178, 219, 259, 273, 274, 279 user event, 107, 108, 112, 117…”