Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors

Vuletic, M.; Pozzi, Laura; Ienne, Paolo

doi:10.1007/978-3-540-30117-2_61

Cited by 5 publications

(3 citation statements)

References 12 publications

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“…Thus, it differs from the traditional paradigm, where RH is used only as a coprocessor. Although the focus of these proposals are not to decrease the overhead caused by the communication costs between processor and coprocessor, same authors shown in [94] a concept which may hide the communication latency by prefetching memory accesses of software threads to the hardware accelerator.…”

Section: Hardware-software Interfacementioning

confidence: 99%

Run-time reconfigurable RTOS for reconfigurable systems-on-chip

Götz

Rettberg

Pereira

et al. 2009

Journal of Embedded Computing

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during my time as a fellow of the working group of Prof. Dr. Franz J. Rammig. Due to a formal agreement between Federal University of Rio Grande do Sul (UFRGS) and University of Paderborn, I had the opportunity to receive a bi-national doctoral degree. Therefore, I had to accomplished, in addition, the PhD Graduate Program in Electrical Engineering of UFRGS. So, I hereby acknowledge, without mention everyone personally, all persons involved in making this agreement possible.

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Section: Hardware-software Interfacementioning

confidence: 99%

Run-time reconfigurable RTOS for reconfigurable systems-on-chip

Götz

Rettberg

Pereira

et al. 2009

Journal of Embedded Computing

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show abstract

“…For example, with communication assistants extended by limited hardware, it can detect memory access patterns generated by hardware accelerators. 10 It can then predict future memory accesses and employ an adequate prefetching technique, attempting to hide memory communication latency. Figure 13 shows how to improve application execution performance without programmer intervention or even knowledge.…”

Section: Dynamic Optimizationmentioning

confidence: 99%

“…For example, Figure 14 shows execution times for the accelerator version based on an improved VMW (with dynamic prefetching implemented in the virtualization layer 10 ). Although running at the same speed, the ADPCM coprocessor with prefetching finishes its task almost twice as fast as without prefetching.…”

Section: Dynamic Optimizationmentioning

confidence: 99%

Seamless Hardware-Software Integration in Reconfigurable Computing Systems

Vuletid

Pozzi

Ienne

2005

IEEE Des. Test. Comput.

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DESPITE THEIR INHERENT POWER and performance drawbacks in comparison with ASICs, FPGAs are increasingly becoming an option for silicon system designers. A way to overcome FPGA shortcomings (such as clock frequencies more than five times slower than those of ASICs and general-purpose processors) is to blend temporal and spatial computing paradigms in systems by using both general-purpose processors and reconfigurable hardware. This is the approach of reconfigurable SoCs (RSoCs) that have recently appeared on the market-for example, Altera Excalibur (http://www.altera.com/literature) and Xilinx Virtex-II Pro (http://www.xilinx.com). Although researchers have reported obtaining significant performance improvements by combining temporal computing (on CPUs) and spatial computing (on FPGAs), two major obstacles hinder the wider acceptance of reconfigurable computing: the lack of a standardized programming paradigm and the lack of portability for codesigned reconfigurable applications.We propose a general solution that overcomes these obstacles by introducing an additional abstraction. We also address the challenge of achieving seamless hardware-software interfacing and portability with minimal performance penalties.Programmers should be able to preserve their hardware-agnostic, high-level programming approaches, even in the presence of application parts executed on FPGAs. On the other hand, hardware designers should be able to write accelerators that can run across different platforms, without any change in the hardware description language (HDL) code. To meet these goals, researchers have proposed sequential programming paradigms (represented by user programs with a single execution thread) for reconfigurable computing systems. For example, addressing hardware-software interfacing problems within a compiler considerably improves the programmability of reconfigurable computing platforms. 1 We introduce a more general, parallel programming paradigm (represented by user programs with multiple execution threads), which requires no changes on the compiler side. Recently, researchers have introduced a hardwarecentered parallel programming model aimed mainly at supporting the design of networking applications. 2Other researchers have proposed a hybrid hardwaresoftware architecture that enables a multithreaded programming model by implementing execution support blocks (for example, thread scheduling and synchronization) in reconfigurable hardware. Our approach is the only one firmly based on the properties that led to general-purpose computing's common acceptance: programming ease and portability. We introduce a multithreaded programming model for reconfigurable computing based on a unified virtualSeamless HardwareSoftware Integration in Reconfigurable Computing Systems Ideally, reconfigurable-system programmers and designers should code algorithms and write hardware accelerators independently of the underlying platform. To realize this scenario, the authors propose a portable, hardwareagnostic programming paradigm, which de...

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Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing

Vuletic¹,

Pozzi²,

Ienne³

Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.

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Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors

Cited by 5 publications

References 12 publications

Run-time reconfigurable RTOS for reconfigurable systems-on-chip

Run-time reconfigurable RTOS for reconfigurable systems-on-chip

Seamless Hardware-Software Integration in Reconfigurable Computing Systems

Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing

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