Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems

Abstract

Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data caches. The embedded operating system will often juggle a changing set tasks in a round-robin fashion, which inevitably results in cache misses due to conflicts between different tasks. Our technique reduces cache misses by continuously monitoring CPU cache misses to grade the performance of running tasks. Through a series of step-wise refinements, our software system tunes the round-robin ordering to find a better temporal sequence for the tasks. This tuning is done dynamically during program execution and hence can adapt to changes in work load or external input stimulus. The benefits of this technique are illustrated using an ARM processor running application benchmarks with different cache organizations and round-robin scheduling techniques.

A dynamic modelling framework for control-based computing system design

“…Each of these cost functions requires to redesign the control strategy, and no control-based selection of the next task is envisioned. On a different page, the authors of [20] reorder the list of tasks to be scheduled with a RR algorithm in an embedded device, with the aim of reducing cache misses. Control is introduced to meet a system requirement by acting on a parameter of a fully functional scheduler, rather than to simplify the design of the entire scheduler.…”

Task scheduling

“…Elsewhere, the Batcher and Walker [2008] reorder the list of tasks to be scheduled with a round robin algorithm in an embedded device, with the aim of reducing cache misses. Also in this case, control is introduced to meet a system requirement by acting on a parameter of a fully functional scheduler, not necessarily designed with that requirement in mind.…”

Control/Architecture Codesign for Cyber-Physical Systems

“…Therefore, on one hand, the cache reuse should be maximized, and on the other hand, the controller must be suitably designed to exploit the shortened sampling periods. There have been some works on cache reuse maximization by employing code positioning during compile time [22,26,32] and also during run time [11], but these cannot directly be applied to embedded control systems as code rearrangement would impact the timing properties, and this is difficult to incorporate while designing the controllers.…”

“…In (11), it is assumed that uOE 1 D 0 for k D 0. Notice that xOEk C 1 depends on both uOEk and uOEk 1, since during the sensor-to-actuator delay, uOEk is not available and uOEk 1 is applied to the plant.…”