Dynamic SEU Sensitivity of Designs on Two 28-nm SRAM-Based FPGA Architectures

Keller, Andrew; Whiting, Tim; Sawyer, Kenneth B.; Wirthlin, Michael

doi:10.1109/tns.2017.2772288

Cited by 23 publications

(11 citation statements)

References 20 publications

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“…In [6] a study of power dissipation effects on a 28nm Xilinx Zynq 7000 FPGA-based System-on-Chip and its neutron sensitivity is presented, demonstrating that the temperature variation caused by a higher operating frequency affects the cross section of the device. In [7] the dynamic SEU sensitivity of designs on Kintex-7 and Stratix V, both of them 28-nm SRAM-based FPGAs, is presented. Also the sensitivities of the design with and without Triple Modular Redundancy (TMR) are compared.…”

mentioning

confidence: 99%

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

Fabero

Mecha

Franco

et al. 2020

IEEE Trans. Nucl. Sci.

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A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed.

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mentioning

confidence: 99%

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

Fabero

Mecha

Franco

et al. 2020

IEEE Trans. Nucl. Sci.

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“…For each device, the raw CRAM FIT rate per megabit is shown. CRAM FIT rate estimates for the Intel Stratix V and the Xilinx Kintex 7 come from [13] and [29] respectively; the number of CRAM bits are taken from vendor tool reports. Since both FPGAs are based on 28-nm technology, their estimated FIT rates are similar.…”

Section: Soft Error Ratesmentioning

confidence: 99%

Impact of Soft Errors on Large-Scale FPGA Cloud Computing

Keller

Wirthlin

2019

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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FPGAs are being used in large numbers within cloud computing to provide high-performance, low-power alternatives to more traditional computing structures. While FPGAs provide a number of important benefits to cloud computing environments, they are susceptible to radiation-induced soft errors, which can lead to silent data corruption or system instability. Although soft errors within a single FPGA occur infrequently, soft errors in large-scale FPGAs systems can occur at a relatively high rate. This paper investigates the failure rate of several FPGA applications running within an FPGA cloud computing node by performing fault injection experiments to determine the susceptibility of these applications to soft-errors. The results from these experiments suggest that silent data corruption will occur every few hours within a 100,000 node FPGA system and that such a system can only maintain high-levels of reliability for short periods of operation. These results suggest that soft-error detection and mitigation techniques may be needed in large-scale FPGA systems.

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“…For planar bulk Si CMOS technologies, the operation voltages decrease and frequencies increase with the feature size scaling down, which make CMOS logic circuits, including FPGAs, more sensitive to SEU [12,13] and contribute more complex and diverse upsets phenomenon happening in cosmic rays and solar flare environments [8,10,11]. In most cases, the complexity of SEUs also affect the effectiveness of hardening designs, especially in million-gate deep submicron FPGA.…”

Section: Introductionmentioning

confidence: 99%

“…In most cases, the complexity of SEUs also affect the effectiveness of hardening designs, especially in million-gate deep submicron FPGA. For commercial FPGAs, in [11][12][13], the significant SEU sensitivities appear, even under low Linear Energy Transfer (LET) heavy-ion radiation. Therefore, more hardening techniques are applied in the deep submicron FPGAs than the submicron hardened FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs

et al. 2019

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The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded RAMs (EBRAMs) and flip-flops. This radiation hardened circuits include large-spacing interlock CRAM cells, area saving debugging logics, the redundant flip-flops cells, and error mitigated 6-T EBRAMs. Heavy ion irradiation test result indicates that the hardened CRAMs had a high linear energy transfer threshold of upset ∼18 MeV/(mg/cm 2 ) with an extremely low saturation cross-section of 6.5 × 10 −13 cm 2 /bit, and 71% of the upsets were single-bit upsets. The combinational use of triple modular redundancy and check code could decline ∼86.5% upset errors. Creme tools were used to predict the CRAM upset rate, which was merely 8.46 × 10 −15 /bit/day for the worst radiation environment. The effectiveness of radiation tolerance has been verified by the irradiation and prediction results.

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Dynamic SEU Sensitivity of Designs on Two 28-nm SRAM-Based FPGA Architectures

Cited by 23 publications

References 20 publications

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

Impact of Soft Errors on Large-Scale FPGA Cloud Computing

Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs

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