Dynamic thermal management for high-performance microprocessors

Brooks, David; Martonosi, Margaret

doi:10.1109/hpca.2001.903261

Cited by 596 publications

(449 citation statements)

References 9 publications

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“…History-based approaches in this sense have been proposed in [30]. The performance impact of many DTM techniques for high-performance microprocessors has been extensively discussed in [6].…”

Section: B Dynamic Thermal Managementmentioning

confidence: 99%

Thermal/performance trade-off in network-on-chip architectures

Zoni

Corbetta

Fornaciari

2012

2012 International Symposium on System on Chip (SoC)

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Abstract-Multi-core architectures are a promising paradigm to exploit the huge integration density reached by highperformance systems. Indeed, integration density and technology scaling are causing undesirable operating temperatures, having net impact on reduced reliability and increased cooling costs. Dynamic Thermal Management (DTM) approaches have been proposed in literature to control temperature profile at run-time, while design-time approaches generally provide floorplan-driven solutions to cope with temperature constraints. Nevertheless, a suitable approach to collect performance, thermal and reliability metrics has not been proposed, yet. This work presents a novel methodology to jointly optimize temperature/performance trade-off in reliable high-performance parallel architectures with security constraints achieved by workload physical isolation on each core. The proposed methodology is based on a linear formal model relating temperature and duty-cycle on one side, and performance and duty-cycle on the other side. Extensive experimental results on real-world use-case scenarios show the goodness of the proposed model, suitable for design-time system-wide optimization to be used in conjunction with DTM techniques.

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Section: B Dynamic Thermal Managementmentioning

confidence: 99%

Thermal/performance trade-off in network-on-chip architectures

Zoni

Corbetta

Fornaciari

2012

2012 International Symposium on System on Chip (SoC)

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“…When the temperature exceeds a predefined threshold, different mechanisms are engaged to reduce the temperature. Such mechanisms include voltage and frequency scaling, fetch throttling [5] among others. A comparison of the various hardware based thermal management schemes is presented in [19].…”

Section: Related Workmentioning

confidence: 99%

“…Most of these techniques are reactive or dynamic in nature. Whenever the on-chip temperature exceeds a predefined threshold, different mechanisms (such as voltage and frequency scaling, fetch throttling [5], scheduling priority adjustments [14], task migrations [10], etc.) can be engaged to reduce the temperature.…”

Section: Introductionmentioning

confidence: 99%

Temperature aware task sequencing and voltage scaling

Jayaseelan

Mitra

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of system design. In this paper, we propose task sequencing as a powerful and complimentary mechanism to voltage scaling in improving the thermal profile of an embedded system executing a set of periodic heterogenous tasks under timing constraints. We first derive the peak temperature of a repeating task sequence analytically and develop a heuristic to construct the task sequence that minimizes the peak temperature. Experimental evaluation shows that our task sequencing heuristic achieves peak temperature within 0.5 o C of the optimal solution and 7.47 o C lower, on an average, compared to the worst sequence for a large range of embedded task sets. We also propose an iterative algorithm that combines task sequencing with voltage scaling to further lower the peak temperature while satisfying the timing constraints. For embedded task sets, our combined task sequencing and voltage scaling approach achieves, on an average, 2.1 o C − 6.94 o C reduction in peak temperature compared to voltage scaling alone.

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“…Due to the end of Dennard scaling [6] (slowed supply voltage scaling), we may become so power-constrained that we are no longer able to power on all transistors at the same time -dark silicon [8]. Runtime factors such as thermal emergencies [2] and power capping [10] further constrain the available chip power. Owing to all the above factors, power budgeting on many-core systems has received considerable attention recently.…”

Section: Introductionmentioning

confidence: 99%

Shared resource aware scheduling on power-constrained tiled many-core processors

Jha

Heirman²,

Falcn³

et al. 2017

Journal of Parallel and Distributed Computing

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Power management through dynamic core, cache and frequency adaptation is becoming a necessity in today's powerconstrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation hardware and the power management algorithms increases. In this paper, we propose a two-tier hierarchical power management methodology to exploit per-tile voltage regulators and clustered last-level caches. In addition, we include a novel thread migration layer that (i) analyzes threads running on the tiled many-core processor for shared resource sensitivity in tandem with core, cache and frequency adaptation, and (ii) co-schedules threads per tile with compatible behavior.

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Dynamic thermal management for high-performance microprocessors

Abstract: With the increasing clock rate and transistor count of today 's microprocessors, power

Cited by 596 publications

References 9 publications

Thermal/performance trade-off in network-on-chip architectures

Thermal/performance trade-off in network-on-chip architectures

Temperature aware task sequencing and voltage scaling

Shared resource aware scheduling on power-constrained tiled many-core processors

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