Dynamic voltage and frequency management for a low-power embedded microprocessor

Nakai, Mitsuki; Akui, S.; Seno, K.; Meguro, T.; Seki, Takahiro; Kondo, Taro; Hashiguchi, A.; Kawahara, Hiroyuki; Kumano, K.; Shimura, M.

doi:10.1109/jssc.2004.838021

Cited by 159 publications

(65 citation statements)

References 6 publications

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“…In DVFS, the clock frequency constraint is dynamically modulated according to application demands in order to improve energy-efficiency. In traditional DVFS, the discrete supply voltage level associated with each discrete frequency level incorporates one-time worst-case aging guardbands [42], [43], hence we name it OWG-DVFS. Here, flavors of our control policies are analyzed in the context of DVFS, viz., PWCA-DVFS, POSA-DVFS, and PRTA-DVFS.…”

Section: Self-tuning Benefits In Dvfsmentioning

confidence: 99%

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-stateaging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-timeaging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.Index Terms-Adaptive supply voltage and clock frequency, circuit aging, energy-efficiency, lifetime reliability.

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Section: Self-tuning Benefits In Dvfsmentioning

confidence: 99%

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Various active control methods such as dynamic voltage and frequency scaling have been studied actively [4]- [6], and have been applied to microprocessors and embedded system, where these methods are relatively easy to apply. However, the operation voltage range of the memory cell array is not as wide as that of digital logic circuits, preventing dynamic voltage scaling methods from being applied to memory [7].…”

Section: Sensing Analysis and Controlmentioning

confidence: 99%

An Autonomous SRAM With On-Chip Sensors in an 80-nm Double Stacked Cell Technology

Sohn

Suh

et al. 2006

IEEE J. Solid-State Circuits

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Abstract-An active solution is proposed to overcome the uncertainty and fluctuation of the device parameters in nanotechnology SRAM. The proposed scheme is composed of sensing blocks, analysis blocks and control blocks. An on-chip timer, temperature sensor, substrate noise detector, and leakage current monitor are used to monitor internal status of chip during operation. From the sensed data, internal supply voltage, internal timing margin from decoding to sensing time, substrate noise from digital area, and low voltage level of wordline are controlled. A 512-kb test SRAM chip, fabricated with an 80-nm double stacked cell technology, shows that average power consumption is reduced by 9% and the standard deviation decreases by 58%.

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“…Considering the ever large-scaled system integration using ever tiny devices, power issues have been the bottleneck for nowadays SoC development. To improve the power usage efficiency and control the power loss [5], many advanced techniques like leakage power reduction, aggressive active and sleep mode control, subthreshold operation [6], and dynamic voltage and frequency scaling (DVFS) [7], [8], have been widely applied in SoC products. For example, Intel [9], IBM [10], Manuscript received December 18, 2015.…”

Section: Introductionmentioning

confidence: 99%

Cooperation between Distributed Power Modules for SoC Power Management

Huang

Lan

2016

IEICE Trans. Electron.

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SUMMARYDistributed power delivery is blooming in SoC power system because the fine-grained power management needs separate power sources to adjust each voltage island dynamically. In addition, dedicated power sources for critical circuit blocks can achieve better signal integrity. To extensively utilize the power modules when they are redundant and idle, this work applies the cooperation concept in SoC power management. The key controller is a mixed-signal estimator that executes the intelligent procedures, like real-time swap the power module depending on its loading and healthy condition, automatically configure the power system with phase interleaving, and support all the peripheral functions. To demonstrate the proposed concept, a prototype chip for voltage down-conversion is implemented. This chip contains four switched-inductor converter modules to emulate the cooperative power network. Each module is small therefore the power efficiency is not optimal for the heavy load. With the cooperation between power modules, the power efficiency is 88% for 300mA load, that is 8.5% higher than the single module operation.

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Dynamic voltage and frequency management for a low-power embedded microprocessor

Cited by 159 publications

References 6 publications

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

An Autonomous SRAM With On-Chip Sensors in an 80-nm Double Stacked Cell Technology

Cooperation between Distributed Power Modules for SoC Power Management

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