Dynamically reconfigurable FFT processor for flexible OFDM baseband processing

Abstract

The Physical layer architectures for the next generation of wireless devices will be characterized by a high degree of flexibility for real-time adaptation to communication conditions variability. OFDM-based architectures are strong candidates for the Physical layer implementation in 5G systems and one of the most important baseband processing operations required by this waveform is the Fast Fourier Transform (FFT). This paper proposes a dynamically reconfigurable FFT processor supporting FFT sizes and throughputs required by the most widely used wireless standards. The FFT reconfiguration was achieved by means of FPGA-based Dynamic Partial Reconfiguration (DPR) techniques, which enables run-time FFT size adaptation according to communication requirements and better resource utilization. The impact of DPR in terms of reconfiguration time and power consumption overhead was evaluated. The obtained results encourage the exploitation of DPR techniques to implement reconfigurable hardware infrastructures for OFDM baseband processing engines.

Dynamically reconfigurable LTE-compliant OFDM modulator for downlink transmission

“…Furthermore, the contribution of dynamic power consumption to the total power consumption increases with the channel bandwidth. Although power measurements were not performed, the comparison between power estimations and measurements performed in [7] shows that the behaviour of power consumption estimations for different modes of operation is similar to what is observed in power measurements. So, based on presented estimations and considering the modes of operation with smallest and largest estimated power consumption (1.4 MHz and 20 MHz), the run-time reconfiguration of the OFDM modulator datapath can bring dynamic power savings of around 101 mW compared to a worst-case implementation.…”

“…This suggests that implementing a multi-mode LTE OFDM modulator by having separate implementations for each mode, or by designing a hardware infrastructure for the worst-case scenario leads to poor energy efficiency. DPR can improve system energy efficiency if the time interval between reconfiguration procedures is much larger than the reconfiguration latency [7], which is a reasonable scenario in the application domain considered for the implemented system.…”

“…Furthermore, upgrades to the current design can be easily done to accommodate other wireless standards. This work is within the scope of the research activities presented in [5] and extends the exploitation of FPGA-based DPR techniques in Software Defined Radio (SDR) and Cognitive Radio (CR) systems initiated in [6] and [7].…”

Field Programmable Gate Array Applications—A Scientometric Review

“…Fast Fourier Transform (FFT) is the most implemented DSP technique in FPGAs, with near to 677 documents related to it. Here, we found CORDIC-based FFT [531][532][533][534][535][536], double-precision floating-point FFT [537], OFDM systems based in FFT [538][539][540][541][542], radix-2 FFT [543,544] and radix-4 FFT [533,[545][546][547] implementations. The Discrete Wavelet Transform (DWT) is a wavelet transform by a certain orthonormal series generated by a discrete wavelet to capture both frequency and location information [548].…”

A Flexible-Channel MDF Architecture for Pipelined Radix-2 FFT

“…In this case, the bypassed stages would be a waste of resources. Another common approach is to employ dynamic partial reconfiguration (DPR) [24]- [25] technology. It is possible to adjust the composition of FFT structure according to the actual operation length at run-time by using DPR, reducing unnecessary resources and power consumption.…”