The 17th Annual SEMI/IEEE ASMC 2006 Conference
DOI: 10.1109/asmc.2006.1638779
|View full text |Cite
|
Sign up to set email alerts
|

Early detection of crystal defects in the device process flow by electron beam inspection

Abstract: In this paper, we describe an inline method to reveal crystal defects in the device fabrication process by voltage contrast detection with an electron beam inspection tool. Suitably designed monitor structures are used to this purpose. The correspondence between bright voltage contrast defects and dislocations connecting the transistor source and drain is demonstrated by selective etching followed by SEM review and by TEM inspection. In addition, it is shown that the voltage contrast defects correlate with the… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Publication Types

Select...
5

Relationship

0
5

Authors

Journals

citations
Cited by 6 publications
(1 citation statement)
references
References 5 publications
0
1
0
Order By: Relevance
“…Causes of bright VC defects include trench to neighboring cell (DT-RX) bridging or connection, trench to trench (DT-DT) bridging into the bulk substrate, and breaks in the trench dielectric which generally occur right below the buried oxide. While the literature contains many works describing the use of VC inspection for in-line detection of electrical fails in semiconductor processing [3][4][5][6][7][8][9], only one work to date discusses VC inspection of eDRAM. In this previous paper, special short loop wafers were used to debug the mask open step [10].…”
Section: Introductionmentioning
confidence: 99%
“…Causes of bright VC defects include trench to neighboring cell (DT-RX) bridging or connection, trench to trench (DT-DT) bridging into the bulk substrate, and breaks in the trench dielectric which generally occur right below the buried oxide. While the literature contains many works describing the use of VC inspection for in-line detection of electrical fails in semiconductor processing [3][4][5][6][7][8][9], only one work to date discusses VC inspection of eDRAM. In this previous paper, special short loop wafers were used to debug the mask open step [10].…”
Section: Introductionmentioning
confidence: 99%