Early detection of systematic patterning problems for a 22nm SOI technology using E-beam hot spot inspection

Patterson, Oliver D.; Ryan, Deborah A.; Monkowski, M.D.; Nguyen-Ngoc, D.; Morgenfeld, Bradley; Lee, Chung-ham; Liu, Chieh-Hung; Chen, Chi-ming; Chen, Shih-tsung

doi:10.1109/asmc.2013.6552748

Cited by 14 publications

(3 citation statements)

References 6 publications

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“…Стремление сократить при этом время вычислений привело к разработке параллельных алгоритмов трансформации [4,5]. Известно, что обнаружение и устранение ошибок в топологии кристалла СБИС на ранних стадиях его проектиро-вания позволяет избежать множества проблем, связанных с затратами и сроками изготовления шаблонов, сократив тем самым время проектирования и производства СБИС [6]. Когнитивная аналитика и визуали-зация могут помочь исключить данную проблему, так как решают задачу извлечения ценности из боль-шого объема данных и преобразования информации в удобный для восприятия и познания человеком формат.…”

Section: рис 1 трансформация топологического слоя для технологии двunclassified

Когнитивная Аналитическая Поддержка Процесса Трансформации Топологического Слоя СБИС Для Технологии Двойного Шаблона

Шахнов¹,

Shahnov²,

Зинченко³

et al. 2017

ППС

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Section: рис 1 трансформация топологического слоя для технологии двunclassified

Когнитивная Аналитическая Поддержка Процесса Трансформации Топологического Слоя СБИС Для Технологии Двойного Шаблона

Шахнов¹,

Shahnov²,

Зинченко³

et al. 2017

ППС

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“…It was shown that VLSI design requires a novel approach, including cognitive human-machine interface. It is obvious that early detection of errors help a designer to overcome problems [13]. In the paper, an approach for contradictions' visualization during SOI VLSI layout decomposition for multiple pattern technology is presented.…”

Section: Introductionmentioning

confidence: 99%

Visual analytics support for the SOI VLSI layout design for multiple patterning technology

Shakhnov

Zinchenko

Макарчук

et al. 2015

2015 6th IEEE International Conference on Cognitive Infocommunications (CogInfoCom)

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In the paper, we discuss visualization techniques for SOI VLSI layout design. Our goal is visual analytics support of time-consuming SOI VLSI layout design process. Our analytics are based on graph models for VLSI layout representation. We propose classification and clustering approaches for data visualization. We illustrate our approach for contradictions visualization for multiple patterning technology case study.

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“…Inter layer defect is always a challenge for inline detection; optical inspection usually cannot provide accurate results for such issues. One of the most effective ways of detecting systematic inter-layer defects is by E-Beam Voltage Contrast (VC) Die-to-Database (D2DB) inspection [1]. E-Beam D2DB can effectively detect an open via and critical dimension (CD) shrinkage by comparing the voltage contrast images of vias to the design layout [2] .…”

Section: Introductionmentioning

confidence: 99%

Net tracing and classification analysis on E-beam die-to-database inspection

et al. 2016

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A novel classification methodology is constructed for Electron Beam (E-Beam) die-to-database (D2DB) inspection results on contact and via layers. It is a design guided defects classification flow that helps to pin-point true defects from a large amount of false alarm defects. Die-to-database E-beam inspection has remarkable features that can help find systematic defects such as Damaged Via and Missing Via; which will be reported as DVC (Dark Voltage Contrast) defects. However, the D2DB result usually reports millions of defects that lie on both 'active via' and 'floating via', the former being defects-of-interest (DOI), and the latter being of little significance. The indiscriminant mixture of DOI (on active vias) and nuisance (on floating vias) is a challenge in the use of D2DB for finding systematic via defects. We overcome this challenge by overlaying the E-beam defect location onto the design layout file (GDS or OASIS) and tracing the path of the via to determine whether or not it connects to the active or diffusion layer. Our proposed flow uses Net Tracing Classification (NTC) feature in Anchor Hotspot Solution (AHS) to classify all the reported DVC defects into different groups, according to the electrical connectivity of the contact. This classification involves multiple interconnected process layers. All the reported DVC defects will be classified into three groups: (1) Real DVC defects, in which the net traces down to active layer; (2) False DVC type 1, in which the net traces down to gate (which is always dark); (3) False DVC type 2, in which the net traces down to floating metal (which is always dark as well). This enhanced defect classification is greatly helpful in separating real DVC contact/via defects from false alarms. It has a secondary benefit of reducing the total number of defects, which is helpful for subsequent in-depth data analysis. In addition, the verified real DVC locations can be used to generate care areas for E-Beam die-to-die (D2D) inspection, which can effectively improve throughput and reduce the turn-around-time (TAT). In this paper, we will discuss a use case at the Vx layer.

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Early detection of systematic patterning problems for a 22nm SOI technology using E-beam hot spot inspection

Cited by 14 publications

References 6 publications

Когнитивная Аналитическая Поддержка Процесса Трансформации Топологического Слоя СБИС Для Технологии Двойного Шаблона

Когнитивная Аналитическая Поддержка Процесса Трансформации Топологического Слоя СБИС Для Технологии Двойного Шаблона

Visual analytics support for the SOI VLSI layout design for multiple patterning technology

Net tracing and classification analysis on E-beam die-to-database inspection

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