Easily testable gate-level and DCVS multipliers

Takach, Andrés; Jha, Niraj K.

doi:10.1109/43.87603

Cited by 28 publications

(9 citation statements)

References 21 publications

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“…Testing of 1-D and 2-D ILA's has been considered in [3]- [5]. Work on C-testability of carry-save multipliers has been addressed in [6] and [7]. In [7], testing of gate level and DCVS logic implementation of carry-save multipliers has been considered.…”

Section: Vlsi Implementation Containing Thousands Of Logic Gatesmentioning

confidence: 99%

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A C-testable carry-free divider

Srinivas

Vinnakota

Parhi

1994

IEEE Trans. VLSI Syst.

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In this paper, the design of a C-testable, highperformance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and is modified to make it C-testable, i.e., it can be exhaustively tested using a constant number of test vectors irrespective of its word-length. Previous C-testable designs considered dividers which used carry-propagate adderskubtractors. These dividers are slow because of their O(W2) computation time (where IT' is the word-length of the divider). High-performance carry-free dividers use carry-free redundant arithmetic adderdsubtractors. Due to this feature, they have O(W) computation time. The on-the-Jly converter used by carry-free dividers to convert the redundant quotient to two's-complement form is shown to be not C-testable. It is modified to be linear-testable (in word-length) instead of exponential time required for exhaustive testing of all possible combinations at its inputs. We conclude that the number of test vectors needed is 99 for C-testing of the divider array and (3W + 10) for linear testing of the converter. The hardware overhead required to make the divider C-testable and the on-theJly converter linear testable is also shown to be nominal.

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Section: Vlsi Implementation Containing Thousands Of Logic Gatesmentioning

confidence: 99%

“…Work on C-testability of carry-save multipliers has been addressed in [6] and [7]. In [7], testing of gate level and DCVS logic implementation of carry-save multipliers has been considered. A C-testable carry-propagate multiplier has been presented in [8].…”

Section: Vlsi Implementation Containing Thousands Of Logic Gatesmentioning

confidence: 99%

A C-testable carry-free divider

Srinivas

Vinnakota

Parhi

1994

IEEE Trans. VLSI Syst.

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“…The design of easily testable array multipliers has been discussed in [9][10][11][12]. The C-testable N x N carry-save and carrypropagate parallel multipliers given, among other multiplier designs, in [9] require 16 and 20 test vectors, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…CFM was used in all the three designs and therefore each cell in the proposed multipliers is tested exhaustively. In [ 12] three Ctestable carry-save array multiplier designs are given. The first design requires 9 test vectors with respect to the CFM; the second design requires 6 test vectors with respect to all single stuck-at faults for a specific gate level implementation of the full adder cell; the third design is given for DCVS implementation and is Ctestable with 6 test vectors which detect all detectable stuck-at, stuck-on and stuck-open faults in the multiplier.…”

Section: Introductionmentioning

confidence: 99%

C-Testable modified-Booth multipliers

et al. 1996

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In this paper the testability of modified-Booth array multipliers for standard cells based design environments is examined for first time. In such cases the structure of the cells may be unknown, thus Cell Fault Model (CFM) is adopted. Two C-testable designs are proposed. A design for an Nx x Ny bits modified-Booth multiplier, which uses ripple carry addition at the last stage of the multiplication, is first proposed. The design requires the addition of only one extra primary input and 38 test vectors with respect to CFM. A second C-testable design is given using carry lookahead addition at the last stage which is the case of practical implementations of modified-Booth multipliers. Such a C-testable design using carry lookahead addition is for first time proposed in the open literature. This second design requires the addition of 4 extra primary inputs. One-level and two-levels carry lookahead adders, are considered. The C-testable design requires 61 test vectors for the former and 73 test vectors for the latter, respectively. The hardware and delay overheads imposed by both C-testable designs are very small and decrease when the size of the multiplier increases.

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“…a C-testable [12], has the constant size of test pattern sets. The Design-forTestability methods and a comprehensive study of testability of multipliers have been discussed in detail in [13][14][15][16] where various fault models of different test pattern set size and variant hardware requirement have been studied. High fault coverage of multipliers is achieved with Cell Fault Model [17].…”

Section: Previous Workmentioning

confidence: 99%

Universal Pattern Set for Arithmetic Circuits

Kumar¹,

Choudhary²,

Bhardwaj³

et al. 2012

IJCA

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The exponential increase in test cost is one of the new challenges being posed by technology scaling. This Paper has been aimed to deal with the issue of testing cost which adds to the chip cost. Here we propose a new pattern set for testing the arithmetic circuits which contains a minimum number of test vectors and easy to generate on the chip and hence supports at-speed testing of the circuit. Though maximum fault coverage is desired but practically generation of test vectors for testing of all the possible defects is not at all feasible. This leads to the modeling of defects as faults which facilitate for simplification of test generation process. Though various fault models have been proposed, the single stuck-at fault model is one of widely accepted model because of having closeness to the actual defects and also, it provide the algorithmic possibilities which, further helps in generation of test vectors. The desired smaller DPM (defective parts per million) levels for devices, creates the need for application of better fault models, which can model the defects in the most accurate fashion. This result in complex fault models which tends to make test generation tedious or even impossible and ultimately increase the test cost. Our motive is to cut down the test cost by finding the minimal number of test vectors for the test. If reduction in the patterns for one module is achieved, it would reduce the overall test cost. We propose universal pattern set which gives good fault coverage for arithmetic circuit with small set of vectors.

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Easily testable gate-level and DCVS multipliers

Cited by 28 publications

References 21 publications

A C-testable carry-free divider

A C-testable carry-free divider

C-Testable modified-Booth multipliers

Universal Pattern Set for Arithmetic Circuits

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