ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI

Sudarshan, Chetan Choppali; Matkar, Nikhil; Vrudhula, Sarma; Sapatnekar, Sachin S.; Chhabria, Vidya A.

doi:10.1109/hpca57654.2024.00058

Cited by 5 publications

(1 citation statement)

References 34 publications

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“…High-end IC markets, such as data centers or the automotive industry, have a growing demand for reliable chips to exploit high-performance computing (HPC) applications and withstand power efficiency, chip longevity, and long-term performance [ 1 , 2 , 3 , 4 ], as well as reduce the carbon footprint of CMOS technologies [ 5 , 6 , 7 ]. However, the rapid downscaling of CMOS technologies, where supply voltages do not scale linearly with device dimensions, results in a concerning increase of IC degradation due to high electric fields that progressively, but inevitably, worsen IC projected reliability and lifetime [ 8 , 9 ].…”

Section: Introductionmentioning

confidence: 99%

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

Diaz-Fortuny,

Saraza-Canflanca,

Bury

et al. 2024

Micromachines

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The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.

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