ECO-Map: Technology remapping for post-mask ECO using simulated annealing

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Chang³

2013

Due to the rapidly increasing design complexity in modern IC designs, metal-only engineering change order (ECO) becomes inevitable to achieve design closure with a low respin cost. Traditionally, preplaced redundant standard cells are regarded as spare cells. However, these cells are limited by predefined functionalities and locations, and they always consume leakage power despite their inputs being tied off. To overcome the inflexibility and power overhead, a new type of spare cells, called metal-configurable gate-array spare cells, are introduced. In this paper, we address a new ECO problem, which performs design changes using metal-configurable gate-array spare cells. We first study the properties of this new ECO problem and propose a new cost metric, aliveness, to model the capability of a spare gate array. Based on aliveness and routability, we then develop two ECO optimization frameworks, one for timing ECO and the other for functional ECO. Experimental results show that our approach delivers superior efficiency and effectiveness.Index Terms-Engineering change order, gate array, mixed integer linear programming

Section: Spare Array Assignmentmentioning

confidence: 96%

ECO Optimization Using Metal-Configurable Gate-Array Spare Cells

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Chang³

2013

“…The timing improvement ti,j, relaxed from the timing satisfaction constraint, is computed assuming the resized gate or inserted buffer i is located at the center of spare array j. Constraint (5) ensures that the total sizes of allocated cells do not exceed the number of free tiles for each spare array. Constraint (6) guarantees that each critical gate is assigned to exactly one spare array. In addition to the routability optimized by the objective function, Constraint (7) limits the pin density of each spare array [22].…”

Section: Spare Array Assignmentmentioning

confidence: 99%

“…Metal-only ECO has been extensively studied in recent literature [2,3,4,5,6,7,8,9,10,11]. To enable metalonly ECO, these works use pre-inserted redundant standard cells as spare cells.…”

Section: Introductionmentioning

confidence: 99%

Timing ECO optimization using metal-configurable gate-array spare cells

Proceedings of the 49th Annual Design Automation Conference

2012

Due to the rapidly increasing design complexity in modern IC designs, metal-only engineering change order (ECO) becomes inevitable to achieve design closure with a low respin cost. Traditionally, preplaced redundant standard cells are regarded as spare cells. However, these cells are limited by predefined functionalities and locations, and they always consume leakage power despite their inputs are tied off. To overcome the inflexibility and power overhead, a new type of spare cells, metal-configurable gate-array spare cells, are considered. Therefore, in this paper, we address a new ECO problem: Timing ECO optimization using metal-configurable gate-array spare cells. We first study the properties for this new ECO problem, propose a new metric, aliveness, to model the capability of a spare gate array, and then develop a timing ECO optimization framework based on aliveness, routability, and timing satisfaction. Experimental results show that our approach delivers superior efficiency and effectiveness.

“…Ho [10]. Then, Modi and Marek-Sadowska use simulated annealing to refine the total wirelength [11]. To avoid the potentially long run time, Jiang et al leverage a robust logic synthesis engine, ABC [16], for technology remapping and adopt stable matching to select spare cells [12].…”

Section: Introductionmentioning

confidence: 99%

Simultaneous functional and timing ECO

Proceedings of the 48th Design Automation Conference

2011

Metal-only ECO is prevalent at design houses to perform incremental design changes to resolve last found functional and/or timing failures. However, it is hard to perform mixed functional and timing changes manually. Prior endeavors focus on functional or timing ECO alone, but we observe that separating them may fail to fix all timing violations. Consequently, this paper presents the first work to perform simultaneous functional and timing ECO. We use an augmented bipartite graph to model both types of ECO. In addition, through comprehensive constant insertion and bridging, the functional capability of each spare cell is enhanced, thus facilitating spare cell selection. Experimental results show that our simultaneous functional and timing ECO engine can successfully resolve mixed functional and timing ECO that is unsolvable by the sequential scheme. Moreover, our engine outperforms the state-of-the-art works for timing ECO with a 117X speedup, and for functional ECO with 6-15% wirelength reductions.