We give new, e ective algorithms for k-way circuit partitioning in the two regimes of k n and k = n, where n is the number of modules in the circuit. We show that partitioning an appropriately designed geometric embedding of the netlist, rather than a traditional graph representation, yields improved r esults as well as large speedups. We derive ddimensional geometric embeddings of the netlist via i a new partitioning-speci c" net model for constructing the Laplacian of the netlist, and ii computation of d eigenvectors of the netlist Laplacian; we then apply iii fast top-down and bottom-up geometric clustering methods.