ECOSCALE: Reconfigurable Computing and Runtime System for Future Exascale Systems

Mavroidis, Iakovos; Papaefstathiou, Ioannis; Lavagno, Luciano; Nikolopoulos, Dimitrios S.; Koch, Dirk; Goodacre, John; Sourdis, Ioannis; Papaefstathiou, Vassilis; Coppola, Marcello; Palomino, Manuel

doi:10.3850/9783981537079_1021

Cited by 26 publications

(28 citation statements)

References 13 publications

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“…These systems offer substantial gains in execution time as well as energy efficiency [1]. Modern high performance computing (HPC) systems thus rely on such heterogeneous systems consisting of traditional processors for performing the sequential tasks and FPGAs used as accelerators performing tasks concurrently.…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

Muslim

Demian²,

et al. 2016

Annals of Computer Science and Information Systems

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Abstract-ModernSoCs are getting increasingly heterogeneous with a combination of multi-core architectures and hardware accelerators to speed up the execution of computeintensive tasks at considerably lower power consumption. Modern FPGAs, due to their reasonable execution speed and comparatively lower power consumption, are strong competitors to the traditional GPU based accelerators. High-level Synthesis (HLS) simplifies FPGA programming by allowing designers to program FPGAs in several high-level languages e.g. C/C++, OpenCL and SystemC.This work focuses on using an HLS based methodology to implement a widely used classification algorithm i.e. k-nearest neighbor on an FPGA based platform directly from its OpenCL code. Multiple fairly different implementations of the algorithm are considered and their performance on FPGA and GPU is compared. It is concluded that the FPGA generally proves to be more power efficient as compared to the GPU. Furthermore, using an FPGA-specific OpenCL coding style and providing appropriate HLS directives can yield an FPGA implementation comparable to a GPU also in terms of execution time.

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Section: Introductionmentioning

confidence: 99%

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

Muslim

Demian²,

et al. 2016

Annals of Computer Science and Information Systems

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“…Other architectures either require a global cache coherent mechanism, which simply cannot scale, or support only DMA operations, which are not efficient for small data transfers, such as messages to synchronize remote threads, or to configure a remote peripheral [13]. The UNIMEM architecture allows moving tasks and processes close to data instead of moving data around.…”

Section: Ecoscale Hardwarementioning

confidence: 99%

A Scalable Runtime for the ECOSCALE Heterogeneous Exascale Hardware Platform

Harvey

Bakanov

Spence

et al. 2016

Proceedings of the 6th International Workshop on Runtime and Operating Systems for Supercomputers

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Exascale computation is the next target of high performance computing. In the push to create exascale computing platforms, simply increasing the number of hardware devices is not an acceptable option given the limitations of power consumption, heat dissipation, and programming models which are designed for current hardware platforms. Instead, new hardware technologies, coupled with improved programming abstractions and more autonomous runtime systems, are required to achieve this goal.This position paper presents the design of a new runtime for a new heterogeneous hardware platform being developed to explore energy efficient, high performance computing. By combining a number of different technologies, this framework will both simplify the programming of current and future HPC applications, as well as automating the scheduling of data and computation across this new hardware platform. In particular, this work explores the use of FPGAs to achieve both the power and performance goals of exascale, as well as utilising the runtime to automatically effect dynamic configuration and reconfiguration of these platforms.

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“…ExaNoDe is also closely collaborating with the ExaNeSt [8] and ECOSCALE [9] H2020 projects. ExaNeSt is investigating how storage, interconnections and cooling systems will have to evolve towards Exascale.…”

Section: Introductionmentioning

confidence: 99%

Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach

Rigo

Pinto

Pouget

et al. 2017

2017 Euromicro Conference on Digital System Design (DSD)

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Abstract-Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able to provide the requested level of density and power efficiency to realise an operational Exascale machine. A disruptive change in the hardware design and integration process is needed in order to cope with the requirements of this forthcoming computing target. This paper presents the ExaNoDe H2020 research project aiming to design a highly energy efficient and highly integrated heterogeneous compute node targeting Exascale level computing, mixing low-power processors, heterogeneous co-processors and using advanced hardware integration technologies with the novel UNIMEM Global Address Space memory system.

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ECOSCALE: Reconfigurable Computing and Runtime System for Future Exascale Systems

Cited by 26 publications

References 13 publications

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL

A Scalable Runtime for the ECOSCALE Heterogeneous Exascale Hardware Platform

Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach

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