EDA Challenges in Nano-scale Technology

Abstract

Since the onset of the 90 nm node the challenges associated with further transistor scaling while maintaining a consistently functional, reliable, and yielding design have increased substantially. While those challenges carry across the spectrum of the manufacturing, the EDA, and the design communities, we believe it is the responsibility and the goal of the EDA industry to deal with those issues as thoroughly and as seamlessly as possible to make those challenges transparent to the designer. In this paper we expose and analyze a plurality of those challenges and briefly go over the solutions EDA tools are offering for dealing with them. We also look forward and cover some of the future challenges associated with the integration of the emerging bottoms-up nano-materials flow with the traditional CMOS top-down process flow which has also entered the nano-era.

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