Edge-states at the onset of a silicon trigate nanowire FET

B., Voisin,; Nguyen, V.-H.; Renard, J.; Jehl, X.; Barraud, S.; Triozon, François; Vinet, M.; Duchemin, Ivan; Niquet, Y.-M.; Franceschi, S. De; M., Sanquer,

doi:10.1109/snw.2014.7348586

2014 Silicon Nanoelectronics Workshop (SNW) 2014

DOI: 10.1109/snw.2014.7348586

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Edge-states at the onset of a silicon trigate nanowire FET

Voisin, B.¹,

V.-H. Nguyen²,

J. Renard³

et al.

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Cited by 2 publications

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“…Electrostatically defined n-type quantum dots have been measured in doped siliconon-insulator based fin-FETs using a number of gate materials [4][5][6][7][8][9][10][11] as well as in intrinsic silicon [12][13][14] and silicon-germanium heterostructures [15]. Spin blockade has been demonstrated in these architectures [16][17][18][19][20] and electron spin relaxation times of the order of seconds [21][22][23] have been reported.…”

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confidence: 99%

Ambipolar quantum dots in intrinsic silicon

Betz

González-Zalba

Podd

et al. 2014

Applied Physics Letters

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We electrically measure intrinsic silicon quantum dots with electrostatically defined tunnel barriers. The presence of both p-type and n-type ohmic contacts enables the accumulation of either electrons or holes. Thus we are able to study both transport regimes within the same device. We investigate the effect of the tunnel barriers and the electrostatically defined quantum dots. There is greater localisation of charge states under the tunnel barriers in the case of hole conduction leading to higher charge noise in the p-regime.Comment: in press at Appl. Phys. Let

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confidence: 99%

Ambipolar quantum dots in intrinsic silicon

Betz

González-Zalba

Podd

et al. 2014

Applied Physics Letters

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“…They consist of a narrow Si channel in silicon-on-insulator substrate with a local top-gate and global back-gate. Spacer elements separate the source and drain electrodes from the top-gate, which in conjunction with surface roughness and remote charges in the gate stack induces two barriers in the potential landscape [10]. We show that at low temperature and low bias electron transport is governed by Coulomb blockade due to these barriers, observable directly e.g.…”

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confidence: 89%

High-frequency characterization of thermionic charge transport in silicon-on-insulator nanowire transistors

Betz¹,

Barraud²,

Wilmart³

et al. 2014

Applied Physics Letters

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We report on DC and microwave electrical transport measurements in silicon-on-insulator CMOS nano-transistors at low and room temperature. At low source-drain voltage, the DC current and RF response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature is accurately fitted by a thermionic model. From the fits we deduce the ratio of gate capacitance and quantum capacitance, as well as the electron temperature.Recent CMOS technology allows for the fabrication of silicon-on-insulator structures of nano-metric size. Depending on fabrication strategy, charge transport in these devices can be quasi-zero-or one-dimensional:Field-effect devices based on narrow silicon channels with spacer regions surrounding the gate can exhibit single-electron-transistor * Electronic address: ab2106@cam.ac.uk (SET) characteristics [1][2][3], whereas gate-allarround nanowires formed in Si fins show 1D behavior, e.g. conductance quantization due to subband formation [4][5][6]. Silicon nanowires on silicon-on-insulator (SOI) substrates have recently been shown to be promising candidates for future low-power and radio frequency (RF) applications [6][7][8][9].

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Edge-states at the onset of a silicon trigate nanowire FET

Cited by 2 publications

References 0 publications

Ambipolar quantum dots in intrinsic silicon

Ambipolar quantum dots in intrinsic silicon

High-frequency characterization of thermionic charge transport in silicon-on-insulator nanowire transistors

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