Effect and procedures of post-exposure bake temperature optimization on the CD uniformity in a mass production environment

Ruck, Kirsten; Weichert, Heiko; Finger, F.; Fleischer, Göran; Hetzer, Dave

doi:10.1117/12.712145

Cited by 7 publications

(4 citation statements)

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“…This is an example of a swing curve with minima and maxima. Wafer numbers 1,2,4, 6,8,10,12,14,16,18,20 and 22 are in first set while wafer 5,7,9,11,13,15,17,19,21,and 23 are in second set. Wafer number 24 is exposed and developed first to find out the center exposure so that the clearing points are in the middle of the 20 by 10 matrix.…”

Section: Methodsmentioning

confidence: 99%

“…They include die-to-die exposure dose optimization [2], focus control [3], grid size adjustment for optical proximity correction [4], writing a multitude of shading elements inside the mask to adjust wafer level CD uniformity [5], and post-exposure bake temperature profile optimization by adjusting heater power in a multi-zone controlled bake plate [6][7][8]. Photoresist thickness variation is one of the major contributors of CD variations [9]. Photoresist is typically spin coated on the wafer and its thickness and uniformity are controlled in part by the spin speed and ramp of spin coaters as well as the volatility of the solvent and the viscosity of the resist [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

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Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Adam

Hashim

2012

2012 International Conference on Statistics in Science, Business and Engineering (ICSSBE)

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The swing curve is depending on the rotation speed of the spinner and the thickness of the photoresist. The thickness should be thick enough to prevent the unexposed area from being etched. It is also need to be uniform so that the image of the pattern to be developed later is in focus at all points on the resist surface. The variation of the photoresist thickness will impact the overall yield of the devices. In this respect, the photoresist thickness needs to be characterized carefully. Therefore, an experiment was set up to determine the right thickness and exposure time to control the critical dimension of the pattern. Photoresist coater and stepper are the main equipment used in this experiment. Positive photoresist is utilized as a pattern transfer medium and elipsometer is employed for film thickness measurement. 24 wafers are used in this experiment. The wafers are separated into 2 sets, each set which consists of 12 wafers have all the thickness variation. This to test the effect of standing resist before exposure and development to the dose-to-clear. The first set is coated, exposed and development. However, the second set is exposed and developed two days after being coated. After the wafer went through the standard cleaning procedure, the wafers were then coated using standard recipes which the spin speed ranging from 6500 to 7600 rpm in 100 rpm incremental with the designated rpm fro 1.2 µm photoresist thicknesses is in the middle. Subsequently, the photoresist thickness of each wafer is measured using elipsometer. Then, the exposure process is done by creating job that will expose the wafers in 20 by 10 arrays of small squares of open field with size 2x2 mm. The exposure is done in such a way where the exposure time will step up to the right and step down to the left from the center after each column. The center of the exposure energy time/step is 240/5. Then the graph is plotted to see the different. From the results we obtained that the minima for the dose-to-clear is at 7200 rpm where the thickness is 1.22 µm. whereby the first set and the second set of wafers produce a slight variation in clearing point.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Adam

Hashim

2012

2012 International Conference on Statistics in Science, Business and Engineering (ICSSBE)

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“…Due to its excellent performance in throughput and precision, OCD has also been used in process equipment qualification and tuning (11). Bake plate optimization for a litho track using OCD showed that WiP (within plate) uniformity improved by 57%, and PtP (plate to plate) uniformity by 93% for L&S patterning process on base Si.…”

Section: Figure 2 Example Memory Structures For Ocd Applicationsmentioning

confidence: 99%

Challenges and Opportunities for Optical CD Metrology in Future Lithography Process

Bao¹,

Ferns²,

Wen³

2009

ECS Trans.

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As the IC industry is progressing towards 32 nm technology, Optical CD metrology will play an important role to help address many challenges in process control. OCD has the unique capability to characterize many critical dimensions in-line for complicated device structures nondestructively. Future process integration requires frequent W2W monitoring and feed forward / feedback control for critical layers. This makes integrated metrology (IM) a key option in process tools, and currently OCD is the only viable option for CD IM. In order to seize these opportunities, many improvements for OCD are need. Optical tools may need to be further optimized for better CD metrology performance. OCD modeling software should be able to model complicated structures and greatly boost ease of use. Furthermore, a well developed IM-SA OCD common platform is needed as the foundation for advanced process and equipment control.

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“…by reducing the difference between population means, and reducing the variance of each population. This can be accomplished by dose control 15 in the scanner, and/or by hot plate temperature control in the coat track 25 . Improvement in resist materials and track optimization 26 are keys to driving defect counts down.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of double-patterning techniques for advanced logic nodes

et al. 2010

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The development of Double-Patterning (DP) techniques continues to push forward aiming to extend the immersion based lithography below 36 nm half pitch. There are widespread efforts to make DP viable for further scaling of semiconductor devices. We have developed Develop/Etch/Develop/Etch (DE2) and Double-Expose-Track-Optimized (DETO) techniques for producing pitch-split patterns capable of supporting semiconductor devices for the 16 nm and 11 nm nodes. The IBM Alliance has established a DETO baseline, in collaboration with ASML, TEL, CNSE, and KLATencor, to evaluate the manufacturability of DETO by using commercially available resist systems. Presented in this paper are the long-term performance results of these systems relevant to defectivity, overlay, and CD uniformity.

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Effect and procedures of post-exposure bake temperature optimization on the CD uniformity in a mass production environment

Cited by 7 publications

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Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Challenges and Opportunities for Optical CD Metrology in Future Lithography Process

Evaluation of double-patterning techniques for advanced logic nodes

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Effect and procedures of post-exposure bake temperature optimization on the CD uniformity in a mass production environment

Cited by 7 publications

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Statistical parameter evaluation for swing curves for the 1.2 &#x03BC;m and 1.8 &#x03BC;m resist thickness in CMOS photolithography process technology

Statistical parameter evaluation for swing curves for the 1.2 &#x03BC;m and 1.8 &#x03BC;m resist thickness in CMOS photolithography process technology

Challenges and Opportunities for Optical CD Metrology in Future Lithography Process

Evaluation of double-patterning techniques for advanced logic nodes

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Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology

Statistical parameter evaluation for swing curves for the 1.2 μm and 1.8 μm resist thickness in CMOS photolithography process technology