Effect of annealing on charge transfer in Ge nanocrystal based nonvolatile memory structure

Abstract

Ge nanocrystals ͑nc-Ge͒ embedded in the gate oxide of the nonvolatile memory structure were synthesized by Ge ion implantation followed by thermal annealing at 800°C for various durations. Large changes in the structural and chemical properties of the Ge + -implanted oxide have been observed, and they have been found to possess a significant impact on the charge transfer in the oxide layer. The distribution and concentration of the nc-Ge and dissolved Ge atoms which serve as both the charge storage and transfer sites in the oxide are affected by the annealing. Two charge transfer mechanisms, i.e., the lateral charge diffusion along the Ge-distributed layer and the charge leakage from the charge storage sites to the Si substrate via the charge transfer sites, have been identified based on the charge retention behaviors. Both mechanisms are enhanced by the annealing as a result of the change in the distribution and concentration of the charge transfer sites.

Applications of Nanotechnology in Next-Generation Nonvolatile Memories

“…In the 30-35 nm thick gate oxide SiO 2 -Si MOSCAP devices, fabricated by Ng et al [13] and Yang et al [16] it is seen that the minimum write voltage drops by about 25-30 % from its original value of 30 V due to nc incorporation in the gate oxide. Such a decrease could be attributed to the lowering of the effective barrier height for electron tunneling in the composite gate dielectric as proposed by Chakraborty et al [125].…”

Electrical Characterization of Ge Nanocrystals in Oxide Matrix

“…Memory devices based on Ge QDs are very promising due to a long charge retention time in the Ge QDs, faster writing/erasing times, and low operating voltages [1,2] Therefore, numerous investigations have been performed on this system, where the influence of different properties on charge trapping and retention were investigated [1][2][3][4][5]. However, the main mechanism of the charge storage is still not completely clear.…”

The effect of the thickness of tunneling layer on the memory properties of (Cu2O)0.5(Al2O3)0.5 high-k composite charge-trapping memory devices

“…which show wonderful charge storage and retention properties as compared with those memory devices with single charge-trapping layer. [25][26][27][28][29][30] Some definite experimental evidences identified that the charge-trapping behaviors in these multilayered memory devices should be ascribed to the inter-diffusion at the interface of different high-k oxides. [25][26][27][28] Recently, some high-k composite oxides have been employed as the charge-trapping dielectrics to achieve the higher density of trapped charges in CTM devices.…”

“…[25][26][27][28][29][30] Some definite experimental evidences identified that the charge-trapping behaviors in these multilayered memory devices should be ascribed to the inter-diffusion at the interface of different high-k oxides.…”