Effect of carrier tunneling on the structure of Si nanowires fabricated by metal assisted etching

Abstract

The metal assisted etching mechanism for Si nanowire fabrication, triggered by doping type and level and coupled with choice of metal catalyst, is still very poorly understood. We explain the different etching rates and porosities of wires we observe based on extensive experimental data, using a new empirical model we have developed. We establish as a key parameter, the tunneling through the space charge region (SCR) which is the result of the reduction of the SCR width by level of the Si wafer doping in the presence of the opposite biases of the p- and n-type wafers. This improved understanding should permit the fabrication of high quality wires with predesigned structural characteristics, which hitherto has not been possible.

Engineering Porous Silicon Nanowires with Tuneable Electronic Properties

“…However, the p-type doped samples with the lower ratio of etching solution (i.e., p + ) and p, see Table 1) show a relatively intense deep at the Si edge which might indicate higher crystalline Si content, compared to the p-type sample etched in the higher oxidizing agent solution (i.e., p 0 ). This agrees with higher oxidation rate via this solution and higher porosity of samples, as reported previously [15]. Furthermore, the n-type sample shows a relatively consistent features with its surface counterpart, though with a slight shift of the Si edge.…”

“…MAcE fabricated silicon nanowires have shown fabrication dependent morphology based on the etching solutions, metal used in the process and the doping type and level (more information can be found in Ref. [15]). An example of scanning electron microscopy (SEM) of p-doped silicon nanowires fabricated via MAcE is shown in Figure 2.…”

“…Crystalline semiconducting nanowires are mainly grown using ultra high vacuum systems via vapor liquid solid (VLS) mechanism by chemical vapor deposition or via diffusion induced VLS in molecular beam epitaxy. On the other hand, porous silicon nanowires are usually produced via metal assisted catalytic etching (MAcE) [15,16]. In both cases, synthesized nanowires are usually doped due either to the doped substrate in the MAcE approach or by contamination via liquid metal droplet adatoms in the VLS method [17,18].…”

“…Recent researches using the VLS approach shows that single Ge crystalline wires could be achieved with particular geometries by the adatom flux dynamics modulation as a function of growth temperature [19,20]. It was previously shown that in MAcE process, silicon nanowires with pre-designed structures can be achieved via modulation of the etching mechanism by the metal and catalytic solution used and the substrate doping type and level [15]. However, the electronic structure and properties of fabricated wires are neither completely investigated nor understood.…”

Rapid formation of single crystalline Ge nanowires by anodic metal assisted etching

“…12 Metal assisted chemical etching (MAcE) is a simple and economically favored method currently used to fabricate Si NWs, offering a large variety of controllability over the Si wires parameters. 13,14 However, MAcE is not effective for Ge NWs fabrication. Although exact phenomena preventing Ge NWs by MAcE are not profoundly comprehended, it can be postulated to be attributed to the following factors.…”