Effect of Deep N-Well Bias in an 850-nm Si Photodiode Fabricated Using the CMOS Process

Chou, Fang-Ping; Wang, Ching-Wen; Li, Zi-Ying; Hsieh, Yi-Hsun; Hsin, Yue-Ming

doi:10.1109/lpt.2013.2248352

Cited by 26 publications

(9 citation statements)

References 15 publications

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“…4 due to higher electric field nearby the NW1 port. Whereas with the 1 V different bias voltage the proposed device doesn't suffer from the problem of high dark current [20] and [21], our device shows 4 times better responsivity and 8 times higher photodetection bandwidth, respectively. Compared with our previous work [15], which is based on the same P + /N-well structure in more advanced CMOS technology, the proposed device shows lower bandwidth mainly because of larger diffusion time due to deeper N-well in 0.25 µm process, but it is expected that higher bandwidth than 7.6 GHz is achieved if the proposed device is realized in the same CMOS technology.…”

Section: Simulation and Measurement Resultsmentioning

confidence: 92%

Bandwidth Improvement of CMOS-APD With Carrier-Acceleration Technique

Lee

Rücker

et al. 2015

IEEE Photon. Technol. Lett.

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We present a silicon avalanche photodetector (APD) based on multiple P + /N-well junctions fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology. In order to overcome the photodetection-bandwidth limitation of the CMOS-APD based on P + /N-well junction, carrieracceleration technique is proposed. With this technique, the photogenerated carriers in the charge-neutral N-well region are accelerated by the extrinsic electric field. To induce the extrinsic electric field inside N-well, the CMOS-APD is designed with multiple junctions to reduce the distance between two different N-well biasing contacts. Its performance is simulated and measured with different bias voltages applied to N-well, and it is demonstrated that the CMOS-APD with the carrier-acceleration technique provides higher photodetection bandwidth.

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Section: Simulation and Measurement Resultsmentioning

confidence: 92%

Bandwidth Improvement of CMOS-APD With Carrier-Acceleration Technique

Lee

Rücker

et al. 2015

IEEE Photon. Technol. Lett.

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“…In order to realize the optical interconnection, it is necessary to integrate optical devices such as light sources, optical waveguides, photodetectors with electronic circuits. A number of researches on Ge photodetectors on Si substrate have been studied for a long wavelength band, while a number of researches on photodetectors fabricated by CMOS process are also studied for short wavelength band [1]- [5], and optical receivers have been demonstrated [6]- [12]. By using CMOS process, it is possible to easily integrate photodetectors and electronic circuits on same Si substrate with low-cost because CMOS process is mature process.…”

Section: Introductionmentioning

confidence: 99%

Wavelength dependence of silicon avalanche photodiode fabricated by CMOS process

Napiah

Hishiki

Iiyama

2017

Optics & Laser Technology

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Avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation by canceling photo-generated carriers in the substrate at the sacrifice of the responsivity. We describe here wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with opened and shorted guard ring structure.

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“…In these applications, short wavelength vertical-cavity surface-emitting lasers (VCSELs) and silicon (Si) photodiodes (PDs) are used for low-cost system configuration. Si PDs fabricated by CMOS process are promising optical devices for easy integration with electronic circuits without any process modification [4][5][6], and avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have been developed for optical interconnection applications [7][8][9][10]. The bandwidth of the CMOS-APD, however, is limited by slow photo-generated carriers from the substrate because all the electrodes are arranged on the surface of the substrate.…”

Section: Introductionmentioning

confidence: 99%

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

Napiah

Gyobu

Hishiki

et al. 2016

IEICE Trans. Electron.

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SUMMARYnMOS-type and pMOS-type silicon avalanche photodiodes (APDs) were fabricated by standard 0.18 µm CMOS process, and the current-voltage characteristic and the frequency response of the APDs with and without guard ring structure were measured. The role of the guard ring is cancellation of photo-generated carriers in a deep layer and a substrate. The bandwidth of the APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. The maximum bandwidth was achieved with the avalanche gain of about 10. Finally, we fabricated a nMOS-type APD with the electrode spacing of 0.84 µm, the detection area of 10 × 10 µm 2 , the PAD size for RF probing of 30 × 30 µm 2 , and with the guard ring structure. The maximum bandwidth of 8.4 GHz was achieved along with the gain-bandwidth product of 280 GHz.

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Effect of Deep N-Well Bias in an 850-nm Si Photodiode Fabricated Using the CMOS Process

Cited by 26 publications

References 15 publications

Bandwidth Improvement of CMOS-APD With Carrier-Acceleration Technique

Bandwidth Improvement of CMOS-APD With Carrier-Acceleration Technique

Wavelength dependence of silicon avalanche photodiode fabricated by CMOS process

Characterizing Silicon Avalanche Photodiode Fabricated by Standard 0.18µm CMOS Process for High-Speed Operation

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