Effect of fluorine implantation on recovery characteristics of p-channel MOSFET after negative bias temperature instability stress

Oh, Sang‐Keun; Kwon, Hyuk-Min; Kwon, Sung-Kyu; Sung, Seung-Yong; Yu, Jungeun; Lee, Ga‐Won; Lee, Hi‐Deok

doi:10.7567/jjap.53.08la03

Cited by 5 publications

(2 citation statements)

References 28 publications

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“…This should introduce F in the gate stack, which is known to passivate oxide traps and reduce the 1/f noise PSD. [38][39][40][41][42][43][44][45][46] The investigated pMOSFETs had a 0.6 nm chemical (ozone) SiO 2 , formed after standard diluted HF clean, 36 ALD cycles of HfO 2 (∼1.8 nm thickness) and TiN gate followed by a fill metal. 28 As illustrated in Fig.…”

Section: Processing Impactmentioning

confidence: 99%

Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

Claeys

O’Sullivan

et al. 2018

ECS J. Solid State Sci. Technol.

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A review is given about the impact of the metal gate (MG) in a High-κ/Metal Gate (HKMG) stack on the quality and defectivity of the dielectric, assessed by low-frequency (LF) noise spectroscopy. In a first part, processing aspects are discussed, like, the thickness of the MG and the implementation of a gate-last approach. In the latter case, it is shown that both the cleaning (or dummy gate removal), the growth of the interfacial SiO 2 layer (chemical versus thermal) and a post-HfO 2 -deposition heat or SF 6 plasma treatment need to be optimized for reducing the gate oxide trap density. In a second part, different MGs are compared from a viewpoint of noise magnitude. It is generally found that alternatives to the standard TiN gate yield better static and noise performance. Results will be presented both for scaled planar and FinFET technologies; the latter fabricated on either bulk or Silicon-on-Insulator (SOI) substrates. Also results on Gate-All-Around NanoWire FETs (GAA NWFETs) fabricated on SOI will be included.

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Section: Processing Impactmentioning

confidence: 99%

Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

Claeys

O’Sullivan

et al. 2018

ECS J. Solid State Sci. Technol.

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show abstract

“…Clearly, there is a need for optimizing the HKMG processing on top of thick SiO 2 . One way of achieving this is by a postdeposition treatment, for example relying on the introduction of F in the gate stack, which is known to reduce the 1/f noise [16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?

Simoen

O’Sullivan

Ritzenthaler

et al. 2018

Semicond. Sci. Technol.

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In order to improve the low-frequency noise of input/output (I/O) p-metal-oxide-semiconductor fieldeffect transistors (pMOSFETs) with a 5 nm SiO 2 /2 nm HfO 2 /5 nm TiN gate stack for DRAM applications, different post-deposition treatments have been investigated. Decoupled Plasma Nitridation with various strengths is compared with an SF 6 plasma anneal. Wafers with and without an Al 2 O 3 cap, serving as a threshold voltage shifter have also been included in the study. It is shown that the best results, i.e. the lowest 1/f noise magnitude, have been found for the SF 6 -treated I/O pMOSFETs, reaching in the best case a value comparable with SiO 2 /polycrystalline silicon reference devices.

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Interface defect engineering for high-performance MOSFETs with novel carrier mobility model: Theory and experimental verification

Ishihara¹,

Nakasaki²,

Matsushita

et al. 2020

AIP Advances

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As the conventional hydrogen-termination method has a limited ability to improve the interface quality between SiO2 and its Si substrate, an alternative termination method to reduce the influence of interface states is necessary. Interface engineering using first-principles calculations to suppress the influence of interface states is proposed based on the findings that silicon with dangling bonds is their primary origin. First-principles calculations indicate that the interface states can be terminated with oxygen when incorporated into the SiO2/Si interface without additional oxidation, which generates other interface states from an appropriate oxygen-anneal process. It is experimentally shown that such an oxygen termination can be realized in slow and low-temperature annealing, and the oxygen-termination method is a promising alternative for hydrogen termination. The stronger Si–O bond introduced from the oxygen termination compared with the Si–H bonds from hydrogen termination ensures a better interface quality. As one oxygen atom terminates two silicon atoms, the oxygen-termination method can efficiently suppress the number of interface defects compared with hydrogen and fluorine termination. The mobility degradation due to the interface states was improved more from oxygen termination than from hydrogen termination because the strength of Coulomb scattering due to Si–O dipoles is reduced from the heavier oxygen mass. Theoretical predictions were verified using experiments, indicating that the oxygen-termination method under appropriately optimized annealing conditions (speed and temperature) is a promising candidate to improve the interface quality by reducing the influence of interface states.

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Effect of fluorine implantation on recovery characteristics of p-channel MOSFET after negative bias temperature instability stress

Cited by 5 publications

References 28 publications

Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

Can we optimize the gate oxide quality of DRAM input/output pMOSFETs by a post-deposition treatment?

Interface defect engineering for high-performance MOSFETs with novel carrier mobility model: Theory and experimental verification

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