2019
DOI: 10.21058/gjet.2019.52002
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Effect of Frequency on Energy Efficient Transceiver Design

Abstract: We have observed the different chip power which are clustered on UART device, example IOs, leakage and total power. This through experiment is done at a frequency of 1 GHz, having a duty cycle of 50% and 1ns time period. We did our experiment with Virtex 4, Virtex 5, Virtex 6, Spartan3 and Spartan 6 FPGA. In the experiment we found Spartan 6 uses the least amount of power among all the FPGA used in the experiment.

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Cited by 2 publications
(1 citation statement)
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“…A power-efficient CU is designed by authors on Artix-7 FPGA by changing its frequency values. With the change in frequency values the power consumption of the CU with FPGA device changes (Kumar et al, 2019d). Stub Series Terminated Logic (SSTL) I/O Standards are used by researchers to improve the power consumption of CU on 40 nm Virtex-6 FPGA.…”
Section: Introductionmentioning
confidence: 99%
“…A power-efficient CU is designed by authors on Artix-7 FPGA by changing its frequency values. With the change in frequency values the power consumption of the CU with FPGA device changes (Kumar et al, 2019d). Stub Series Terminated Logic (SSTL) I/O Standards are used by researchers to improve the power consumption of CU on 40 nm Virtex-6 FPGA.…”
Section: Introductionmentioning
confidence: 99%