Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

Abstract

The holding voltage of electrostatic discharge (ESD) protective structure is the critical parameter to determine the latch-up performance of the protecting device, but the thermal change of ESD device parameters exposes the protecting device to latch-up risk in high ambient temperature. In this paper, the holding characteristics of the ESD protection device under various ambient temperatures ranging from 30 to 195℃℃ are studied. The investigated ESD structure is the NMOS transistors fabricated with the 0.18 μm partially depleted silicon-on-insulator (PDSOI) process. The ESD characteristics of the device are measured by the transmission line pulse (TLP) test system at different ambient temperatures. The test results show that the holding voltage (<i>V</i><sub>H</sub>) decreases with the increasing temperature. TCAD simulation is carried out to support and analyze the experiment results, and the same trend of <i>V</i><sub>H</sub> versus temperature is obtained. Through the analysis of simulation results and theoretical derivation, the underlying physical mechanisms related to the effects of temperature on <i>V</i><sub>H</sub> and holding current (<i>I</i><sub>H</sub>) are discussed in detail. When the Drain is subject to the same current pulsing, Source and Body is grounded, the distributions of current density, electric potential, and injected electron density of NMOS under various temperatures are extracted and analyzed. When the Drain, Source, and Body are grounded, the distributions of the electrostatic field under various temperatures are extracted and analyzed. The distributions of electric potential in NMOS indicate that voltage drop on the Drain-Body junction (<i>V</i><sub>DB</sub>) is affected by ambient temperature significantly, and the variation of <i>V</i><sub>DB</sub> dominates the variation trend of <i>V</i><sub>H</sub> with increasing temperature. The decreasing electrostatic field and increasing injected electron density with decreasing temperature contribute to the decreasing <i>V</i><sub>DB</sub>. The trend of <i>I</i><sub>H</sub> and parasitic Body resistance (<i>R</i><sub>Body</sub>) weakens the temperature dependence of the <i>V</i><sub>H</sub>. The current gain of parasitic bipolar transistor (<i>β</i>) decreases with growing ambient temperature, which is the main contributor to the decreasing <i>I</i><sub>H</sub>. Therefore, increasing <i>I</i><sub>H</sub> and <i>R</i><sub>Body</sub> is helpful to reduce the temperature dependence of the latch-immune ESD protection structure.