Effect of intrinsic stress from a nanoscale high-dielectric constant gate oxide on strain in a transistor channel

Abstract

The author propose using a nanoscale gate dielectric directly as stressor to alter the strain field in a transistor channel. Using experimentally determined intrinsic stress generated from a gate dielectric, they analyze the strain field in a channel by finite element methods simulation. Analysis shows that the gate dielectric induced strain can be as large as 0.2% corresponding to ∼25% hole mobility enhancement. The results predict that performance improvement in semiconductor devices can be achieved by choosing proper dielectric film deposition conditions and optimizing geometric dimensions. The approach is compatible with other methods presently utilized for generating local strains as well as high-mobility semiconductor channel layers.