Effect of ion implantation energy for the synthesis of Ge nanocrystals in SiN films with HfO2/SiO2 stack tunnel dielectrics for memory application

Abstract

Ge nanocrystals (Ge-NCs) embedded in SiN dielectrics with HfO2/SiO2 stack tunnel dielectrics were synthesized by utilizing low-energy (≤5 keV) ion implantation method followed by conventional thermal annealing at 800°C, the key variable being Ge+ ion implantation energy. Two different energies (3 and 5 keV) have been chosen for the evolution of Ge-NCs, which have been found to possess significant changes in structural and chemical properties of the Ge+-implanted dielectric films, and well reflected in the charge storage properties of the Al/SiN/Ge-NC + SiN/HfO2/SiO2/Si metal-insulator-semiconductor (MIS) memory structures. No Ge-NC was detected with a lower implantation energy of 3 keV at a dose of 1.5 × 1016 cm-2, whereas a well-defined 2D-array of nearly spherical and well-separated Ge-NCs within the SiN matrix was observed for the higher-energy-implanted (5 keV) sample for the same implanted dose. The MIS memory structures implanted with 5 keV exhibits better charge storage and retention characteristics compared to the low-energy-implanted sample, indicating that the charge storage is predominantly in Ge-NCs in the memory capacitor. A significant memory window of 3.95 V has been observed under the low operating voltage of ± 6 V with good retention properties, indicating the feasibility of these stack structures for low operating voltage, non-volatile memory devices.

Atomic scale observation of phase separation and formation of silicon clusters in Hf higk-κ silicates

“…16,17 Meanwhile, to our knowledge, no information was obtained about decomposition process for films as (HfO 2 ) x (SiO 2 ) y with x þ y 6 ¼ 1. As evoked previously, the formation of Si-or Ge-NCs (or ncs) requires an annealing treatment at 900-1100 C. 10,18,25 If these NCs (or ncs) have to be grown in the Hf-silicate matrix, the thermal behaviour of this latter element has to be taking into account. 5,14,15,20 In this paper, we present a specific approach developed to fabricate Hf-silicate dielectrics with embedded Si-ncs.…”

“…11,12 After this step, a specific annealing treatment is carried out to form NCs (or ncs) inside high-j host. [10][11][12] It is worth to note that up to now neither Si-NCs nor Si-ncs formation in Hf-silicate host was demonstrated. To explain this fact, one can refer to a Hf-Si-O phase diagram.…”

“…Initially, silicon (or germanium) is incorporated into high-j host. For this purpose, different techniques are used, for instance, Si(Ge) ion implantation 10 or deposition of thin Si(Ge)-based layer sandwiched between the high-j layers. 11,12 After this step, a specific annealing treatment is carried out to form NCs (or ncs) inside high-j host.…”

Si and Ge nanocrystals for future memory devices

“…10 shows the charge retention characteristics of both layers from the application of a stress voltage of 76 V (positive for electron charging and negative for hole charging) for 3 s. The retention curves exhibit a logarithmic dependence on the waiting time. For the Si-NCs dielectric stacks, the electron loss is very fast during the first seconds but still shows a memory window of 1.1 V after 10 4 s. Charge retention is enhanced in the case of Ge-NCs dielectric stacks, which exhibit a memory window of 2.4 V after a waiting time of 10 4 s and a 10 years extrapolated window of about 1.1 V. As compared to the Si-NCs samples, this enhanced charge retention could be attributed to charge confinement in Ge-NCs [56].…”

“…To overcome the above limitation, alternative structures have been recently proposed, where HfO 2 is used as tunnel oxide and the NCs are embedded in a SiN overlayer [56]. Using the ULE-IBS method formation of Si and Ge-NCs in a SiN matrix located onto a thin stack of dielectrics comprising a HfO 2 layer and an oxide interfacial layer has been demonstrated (see Fig.…”