Effect of layout orientation on the performance and reliabiltiy of high voltage N-LDMOS in standard submicron logic STI CMOS process

Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the high voltages applied to the N-LDMOS device hot carrier (HC) degradation is a real reliability concern. In high power applications N-LDMOS devices are often implemented in transistor arrays where the basic cell is a dual gate single drain device. This paper focuses on understanding unusual N-LDMOS HC results in which single gate devices had significantly better HC performance than dual gate devices.

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Effect of layout orientation on the performance and reliabiltiy of high voltage N-LDMOS in standard submicron logic STI CMOS process

Cited by 7 publications

References 4 publications

The Impact of High-voltage Drift N-well and Shallow Trench Isolation Layouts on Electrical Characteristics of LDMOSFETs

The Impact of High-voltage Drift N-well and Shallow Trench Isolation Layouts on Electrical Characteristics of LDMOSFETs

An electrical-aware parametric DFM solution for analog circuits

Effect of Photo Misalignment on N-LDMOS Hot Carrier Device Reliability

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