Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances

Pandey, Archana; Raycha, Swati; Maheshwaram, Satish; Manhas, S. K.; Dasgupta, S.; Saxena, Ashok Kumar; Bulusu, Anand

doi:10.1109/ted.2013.2291013

Cited by 25 publications

(19 citation statements)

References 12 publications

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“…There may also be some additional benefit from the greater quantum confinement in the quantum dot as compared to the quantum well gain media presumed in our scaling. 35 Actual energy per bit can be lower because it is not necessary to swing over the entire bias voltage to run QCSE devices [41]. Sub-femtojoule per bit can be deduced in that case for this modulator.…”

Section: Optical Concentration Factormentioning

confidence: 98%

“…For the modulator with 1 μm 3 active volume, the 5 fJ is comparable with the operating energy (including the bias field 35 ) for a compact QCSE modulator [41], [78].…”

Section: Optical Concentration Factormentioning

confidence: 99%

“…Energy per bit References and notes Wireless data 10 -30μJ [31] Internet: access 40 -80nJ [8]; (a),(b) Internet: routing 20nJ [9]; (c) Internet: optical WDM links 3nJ [32]; (d) Reading DRAM 5pJ [5]; (e) Communicating off chip 1 -20 pJ [5], [15], [16] Data link multiplexing and timing circuits ~ 2 pJ [24] Communicating across chip 600 fJ [5]; (f) Floating point operation 100fJ [5]; (g) Energy in DRAM cell 10fJ [33]; (h) Switching CMOS gate ~50aJ -3fJ [4], [6], [34], [35]; (i) 1 electron at 1V, or 1 photon @1eV 0.16aJ (160zJ) WDM -wavelength division multiplexing DRAM -dynamic random-access memory CMOS -complementary metal-oxide-semiconductor transistor (a) Uses projections to 2016 from [8] (b) Presumes wired connections (optical or electrical) to the network (c) Total for 20 "hops" per internet connection, and derating energies from the 2008 numbers in [9] using a factor of 0.74 per year (from [8]) for improved electronics energy efficiency. (d) Total for 20 "hops" per internet connection, and using projections to 2016 in [32] (e) Rounded sum of the DRAM access and interface energies as projected for 2017 in [5], for off-chip DRAM (f) Based on 2017 projects in [5] for a 10mm line on the chip (g) Double-precision fused multiply-add (floating-point) operation using the projection in [5] of ~ 6.5 pJ in 2017 for this 64-bit operation to calculate energy per bit.…”

Section: Operationmentioning

confidence: 99%

“…Then from Eq. (35), the number of orthogonal spatial channels between the surfaces is limited by diffraction to…”

Section: J Calculations Of Number Of Channelsmentioning

confidence: 99%

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Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Miller

2017

J. Lightwave Technol.

602

406

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Optics offers unique opportunities for reducing energy in information processing and communications while simultaneously resolving the problem of interconnect bandwidth density inside machines. Such energy dissipation overall is now at environmentally significant levels; the source of that dissipation is progressively shifting from logic operations to interconnect energies. Without the prospect of substantial reduction in energy per bit communicated, we cannot continue the exponential growth of our use of information. The physics of optics and optoelectronics fundamentally addresses both interconnect energy and bandwidth density, and optics may be the only scalable solution to such problems. Here we summarize the corresponding background, status, opportunities, and research directions for optoelectronic technology and novel optics, including sub-femtojoule devices in waveguide and novel 2D array optical systems. We compare different approaches to low-energy optoelectronic output devices and their scaling, including lasers, modulators and LEDs, optical confinement approaches (such as resonators) to enhance effects, and the benefits of different material choices, including 2D materials and other quantum-confined structures. With such optoelectronic energy reductions, and the elimination of line charging dissipation by the use optical connections, the next major interconnect dissipations are in the electronic circuits for receiver amplifiers, timing recovery and multiplexing. We show we can address these through the integration of photodetectors to reduce or eliminate receiver circuit energies, free-space optics to eliminate the need for timing and multiplexing circuits (while also solving bandwidth density problems), and using optics generally to save power by running large synchronous systems. One target concept is interconnects from ~ 1 cm to ~ 10 m that have the same energy (~ 10fJ/bit) and simplicity as local electrical wires on chip.

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Section: Optical Concentration Factormentioning

confidence: 98%

“…For the modulator with 1 μm 3 active volume, the 5 fJ is comparable with the operating energy (including the bias field 35 ) for a compact QCSE modulator [41], [78].…”

Section: Optical Concentration Factormentioning

confidence: 99%

Section: Operationmentioning

confidence: 99%

“…Then from Eq. (35), the number of orthogonal spatial channels between the surfaces is limited by diffraction to…”

Section: J Calculations Of Number Of Channelsmentioning

confidence: 99%

See 2 more Smart Citations

Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Miller

2017

J. Lightwave Technol.

602

406

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“…C ONTINUOUS scaling of MOSFET technology has enhanced the role of parasitic capacitances in circuit performance [1], [2]. In sub-14-nm technology node devices, the parasitic capacitances have started to dominate the total MOSFET capacitance [3], [4], which deteriorates both the speed and the power consumption of integrated circuits [5].…”

Section: Introductionmentioning

confidence: 99%

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Hiblot

Rafhay

Bœuf

et al. 2015

IEEE Trans. Electron Devices

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In this paper, the main MOSFET parasitic capacitances of planar devices (i.e., bulk, Fully depleted silicon-on-insulator (FDSOI), and planar double gate) are computed using two successive conformal mapping transforms. First, the structure is mapped to the real axis of the complex plane, and then the second transform, deduced directly from the Schwarz-Christoffel theorem, reduces the capacitance to the trivial parallel electrodes case. This second step involves elliptic integrals, which provide a generic expression for all parasitic capacitances. This method is later compared against other models based on conformal mapping. Finally, the results are validated with finite-element method simulations of the inner and outer fringe capacitances in different architectures, including metallic contacts and raised and faceted junctions.Index Terms-CMOS, compact model, conformal mapping, electrostatic, elliptic integrals, Model for Assessment of CMOS Technologies and Roadmaps (MASTAR), MOSFET, parasitic capacitance, roadmap.

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Performance Analysis of Sub 10 nm Double Gate Circular MOSFET

Sagar

Maheshwaram

2022

Silicon

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Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances

Cited by 25 publications

References 12 publications

Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Performance Analysis of Sub 10 nm Double Gate Circular MOSFET

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