Effect of margin widths on the residual stress in a multi-layer ceramic capacitor

Park, Jong‐Sung; Shin, Hyunho; Hong, Kug Sun; Jung, Hyun Suk; Lee, Jung‐Kun; Rhee, Kyong-Yop

doi:10.1016/j.mee.2006.06.008

Cited by 9 publications

(3 citation statements)

References 9 publications

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“…It is interesting that peak values of σ 1 increase monotonically during the soldering process as the width of the lateral margin increases, while peak values of σ 1 are relieved monotonically by the bending process as the width of the lateral margin increases. The variation in thermal residual stress displays the same trend as those found in the sintering process . Secondly, different solder heights, which are measured from the base of the dielectric ceramic to the uppermost point of the solder, influence the peak value of σ 1 .…”

Section: Discussionsupporting

confidence: 55%

“…As the importance of miniaturization of the MLCC chip, the number of capacitor layers must also increase and the thicknesses of the ceramic/electrode layers must decrease. The characterization of residual stresses in MLCCs has been presented in a number of studies; however, most were primarily concerned with the residual stresses induced by the cooling process that follows sintering. Few groups have investigated the influences of the residual stresses induced by the termination firing and soldering processes, which are required to mount the MLCC onto the circuit board .…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Finite Element Analysis and Design of Thermal–Mechanical Stresses in Multilayer Ceramic Capacitors

Huang¹,

Chen²,

Chen

et al. 2013

Int J Applied Ceramic Tech

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A three‐dimensional finite element model describing the thermal–mechanical stress distribution in multilayer ceramic capacitors (MLCCs) during termination firing, soldering, and bending tests is presented. Numerical results indicate that the thermal residual stresses originating from the soldering process are approximately one‐fifth to half of the magnitude of the flexural stresses at the crack occurrence during the board flex test. The peak tensile stress from numerical simulations correlates with the crack initiation site observed in situ in board flex tests. The effects of inner electrode number, solder wicking height, lateral margin length, and the thickness of nickel in the termination component on mechanical failure during the board flex test are also investigated. Numerical results demonstrate that the maximum tensile stress could be effectively relieved by increasing the length of the lateral margin. In addition, a judicious combination of the solder wicking height and nickel termination thickness can further diminish the peak tensile stress during the board flex test. Finally, better design criteria are also developed by modifying the geometric parameters of MLCCs using Taguchi orthogonal arrays to decrease the peak tensile stresses that occur during board flex tests.

show abstract

Section: Discussionsupporting

confidence: 55%

Section: Introductionmentioning

confidence: 99%

Finite Element Analysis and Design of Thermal–Mechanical Stresses in Multilayer Ceramic Capacitors

Huang¹,

Chen²,

Chen

et al. 2013

Int J Applied Ceramic Tech

View full text Add to dashboard Cite

show abstract

“…[2][3][4][5] For example, Den Toonder et al 3 calculated the residual stress during the cool-down step in the sintering process using a finite element method (FEM) and compared their results with actual measurements. Park et al 2,4 and Jiang et al 5 studied the effects of residual stress by varying the layer number, thickness, and margin widths. Going beyond residual stress, Park et al 6 simulated the thermomechanical stresses during termination firing, soldering, and board flex testing.…”

Section: Introductionmentioning

confidence: 99%

Numerical analysis of dielectric ceramic and void containing Ni electrode layers of multilayer ceramic capacitors

Lee

Kim

et al. 2012

Journal of Composite Materials

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In this article, we performed a numerical analysis of dielectric ceramic and Ni electrode layers with voids in a multilayer ceramic capacitor using the finite element method. To numerically analyze a multilayer ceramic capacitor composed of several hundred ceramic and Ni layers, we defined a unit cell, and equivalent material properties from the ceramic and Ni layers were calculated by the homogenization method. We predicted the deformation of the overall multilayer ceramic capacitor from that of a unit cell with equivalent material properties. Voids in the Ni layer, produced during the manufacturing process, were taken into consideration. Because both ceramic and Ni layers are viscoelastic and are in contact with each other, viscoelastic and contact analyses were carried out using the commercial software ANSYS. Dynamic mechanical analysis was used to determine the viscoelastic material properties of the ceramic and Ni layers. We compared the elastic results with the viscoelastic results to determine the viscoelastic characteristics of a multilayer ceramic capacitor. The surface roughness of a multilayer ceramic capacitor was measured by confocal microscopy to verify the reliability of the numerical analysis. The experimental results showed reasonable agreement with the model-based results.

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Analysis for deformation behavior of multilayer ceramic capacitor based on multiscale homogenization approach

Lee

Kang

2018

J Mech Sci Technol

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Effect of margin widths on the residual stress in a multi-layer ceramic capacitor

Cited by 9 publications

References 9 publications

Finite Element Analysis and Design of Thermal–Mechanical Stresses in Multilayer Ceramic Capacitors

Finite Element Analysis and Design of Thermal–Mechanical Stresses in Multilayer Ceramic Capacitors

Numerical analysis of dielectric ceramic and void containing Ni electrode layers of multilayer ceramic capacitors

Analysis for deformation behavior of multilayer ceramic capacitor based on multiscale homogenization approach

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