Effect of Module Order on VLSI Floor Planning using Simulated Annealing

Desai, A.M.; Wali, Uday

doi:10.1109/conecct50063.2020.9198543

Cited by 3 publications

(1 citation statement)

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“…An iterative approach is used; relaxation of modules and then simulated annealing is used to generate a near optimal solution. The best floor-plan can be chosen from the generated near optimal solutions (Ashwini Desai and Uday Wali, 2020). A modified SA algorithm is discussed by yifan Weng et al, (2019).…”

Section: Introductionmentioning

confidence: 99%

VLSI Floorplan Area Optimization using Swarm Intelligence

Desai¹

2020

Biosci. Biotech. Res. Comm

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Floor-planning is a very important stage in the VLSI Physical design process. It determines size, performance, reliability and yield of the VLSI chips. VLSI floor-planning is considered as NP-hard in computational point of view. The modern VLSI technology is associated with fixed outline floor-plan constraint and the objective is to minimize the area and wire-length between the modules. In this paper Particle Swarm Optimization (PSO) algorithm is proposed. PSO is used to optimize the floor-plan area and to represent the floor-plan for non-slicing structure, where area is the physical quantity that is considered for optimization. PSO is an effective swarm intelligence search method which explores the search space during the optimization process to find a near optimal solution. The proposed PSO algorithm is tested with the Microelectronics Centre of North Carolina benchmark circuits (MCNC). The obtained results show that the proposed PSO has better optimization of area of floor-plan with optimal run-time compared to other existing optimization schemes. An area improvement of 7.8% and 11.9% is obtained with MCNC benchmarks ami33 and XEROX10 as compared to the existing methods.

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Section: Introductionmentioning

confidence: 99%