Effect of oxide traps on channel transport characteristics in graphene field effect transistors

Abstract

A semiempirical model describing the influence of interface states on characteristics of gate capacitance and drain resistance versus gate voltage of top gated graphene field effect transistors is presented. By fitting our model to measurements of capacitance–voltage characteristics and relating the applied gate voltage to the Fermi level position, the interface state density is found. Knowing the interface state density allows us to fit our model to measured drain resistance–gate voltage characteristics. The extracted values of mobility and residual charge carrier concentration are compared with corresponding results from a commonly accepted model which neglects the effect of interface states. The authors show that mobility and residual charge carrier concentration differ significantly, if interface states are neglected. Furthermore, our approach allows us to investigate in detail how uncertainties in material parameters like the Fermi velocity and contact resistance influence the extracted values of interface state density, mobility, and residual charge carrier concentration.

Enhanced Intrinsic Voltage Gain in Artificially Stacked Bilayer CVD Graphene Field Effect Transistors

“…The extracted electron & hole mobility values in the channel region were found to be 830 cm 2 /V.s and 610 cm 2 /V.s, respectively. The electron‐hole mobility asymmetry in GFETs is well reported and can be attributed to factors like contact induced doping, field induced doping or phonon‐induced scattering . The close fit with experimental data in Figure could only be obtained when the factors describing the Dirac point shift due to back‐gate voltage are reduced to a non‐physical value, because compared to a Bernal stacked bilayer case, the Dirac point shift in our devices is much smaller.…”

A 400-GHz Graphene FET Detector

“…where q is electron charge, μ is mobility, and C g is the gate capacitance per unit area which, in general, includes the gate dielectric, and quantum and interface capacitances [20]. Because of this, the maximum of ΔU at ∂ΔU/∂V g = 0 reads as follows:…”

Effects of Self-Heating on ${f}_{\text{T}}$ and ${f}_{\text{max}}$ Performance of Graphene Field-Effect Transistors

“…The charge carrier concentration constitutes the sum of thermally generated charge carriers n th , residual charge carriers n 0 due to the charged impurity doping [51], and gate-induced charge carriers n g . In our calculations, n 0 = 1 •10 16 m −2 and n th +n g dependent on the position of the Fermi level is calculated as in [43], and the relation between the gate bias V gs and E F is established as V gs = (Q g + Q ox )/C ox + E F , where Q g is the charge in the graphene sheet and Q ox is the charge in the oxide, which constitute the charge trapped in deep traps and interface states [43]. Fig.…”