We report on the fabrication of silicon oxynitride (SiON ~ 5.34 nm) as a sacrificial layer for an n-Si/ALD-ZrO2 gate stack followed by the postdeposition annealing (PDA) of ZrO2 in argon ambient. The surface morphological studies include atomic force microscopy and field emission scanning electron microscopy whereas the thicknesses of the grown films were confirmed by both ellipsometry and FESEM cross-sectional studies. The surface topographical study suggests an r.m.s. roughness of 0.796 nm for nano zirconia film after rapid thermal annealing (RTA). Electrical parameters such as dielectric constant k, effective oxide thickness EOT, leakage current density J, effective oxide charge Qeff and series resistance Rs were extracted through C-V and I-V measurements and the determined values of k, J, EOT, Qeff and Rs at 100 kHz are 26, 8.75 × 10 -9 A/cm 2 , 2.5 nm, 0.42 × 10 13 cm -2 and 4.54 kΩ, respectively. The concept of an SiON SL has significantly suppressed the existing unacceptable gate leakage current and interfacial traps owing to appropriate segregation of nitrogen at the interface of SiON/ZrO2. Moreover, PDA of ZrO2 film in Ar-ambient at 500 o C has reduced the r.m.s roughness and also contributed to the overall reduction of gate leakage current density, thereby, making the ALD-ZrO2/SiON gate stack quite attractive for advanced CMOS devices.