Effect of post-deposition annealing temperature on RF-sputtered HfO2 thin film for advanced CMOS technology

Effects of post deposition annealing, interface states and series resistance on electrical characteristics of HfO2 MOS capacitors

“…The Q eff value of MOS capacitor annealed at 550°C that shows a good behaviour is lower than the value (4.32 9 10 12 ) reported by Khairniar et al [9]. One of the most important parameters affecting on C-V characteristics is density of the interface states which can be found using following equation [9,22]:…”

“…High annealing temperature may leads to the breaking of metastable Hf-Si bonds and the HfSi x O y may be observed as dominant components at the interfacial layer [13]. Besides, present of interfacial layer leads to the reduction of effective oxide capacitance of MOS capacitor [9,17]. In addition to interfacial layer, another reason of the decreasing capacitance may be leakage current.…”

“…It has been reported that the SiO 2 film thickness less than 1.2 nm lead to serious leakage current due to the direct tunneling of electrons [3][4][5][6]. During recent years, the studies on the investigation of the electrical properties of the high-k dielectric materials as gate insulator such as ZrO 2 [7], Al 2 O 3 [8], HfO 2 [9,10] have been extensively increased with the aim of designing the high performance. Among the high-k dielectrics, HfO 2 has been reported as the most promising candidate due to their attractive properties such as high dielectric constant [11], large band gap [12], and good thermodynamic stability [4].…”

“…But, it is difficult to form a perfect HfO 2 / Si interface compared to the SiO 2 /Si because Hf-silicate/Hf-O-Si formation and SiO 2 layer generally occurs during the initial stage of the dielectric deposition or after PDA process [6,[13][14][15][16]. Moreover, the phase transition of the HfO 2 film, from amorphous to crystalline, occurs with the increasing in annealing temperature and so, the electrical properties of MOS capacitor such as leakage current, capacitance values, flat band voltage are influenced [9,13]. For these reasons, the determination of the optimum PDA conditions is quite important to fabricate high quality devices.…”

“…The results of these studies show that the crystallization temperature of HfO 2 gate dielectric is improved by the nitrogen ambient during PDA process. Moreover, A few studies on the investigation of capacitance-voltage (C-V) and conductance-voltage (G/x-V) characteristic curves of MOS capacitor with HfO 2 annealed at different temperature were reported and, the obtained results show that the PDA temperature strongly influences the behaviours of C-V and G/x-V curves [4,9,13,17,18]. However, C-V curve behaviours of devices annealed at similar temperature range are not consistent with each other.…”