2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) 2014
DOI: 10.1109/smelec.2014.6920825
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Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

Abstract: This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (V th ). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO … Show more

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