Effect of RRC on SOI MOSFET to improve the SCE

Mishra, Sandip K.; Lenka, Annada Shankar; Mohanty, Soumya S.; Bhanja, Urmila; Mishra, Guru Prasad

doi:10.1109/devic.2017.8074008

Cited by 5 publications

(1 citation statement)

References 12 publications

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“…[12][13][14][15] By incorporating this technology in SOI-MOSFET, ie, introducing a groove between source and drain regions, penetration of drain side depletion region is less towards the source side thus minimizes the hot-carrier immunity and punch through effects. [16][17][18][19][20] Different techniques like plasma etching, shallow trench isolation, and reactive ion etching have been adopted for fabrication of grooved gate MOSFETs. 12,16 Device scaling reduces the gate control on threshold voltage.…”

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confidence: 99%

Variation of source gate workfunction on the performance of dual material gate rectangular recessed channel SOI‐MOSFET

Mishra

Bhanja

Mishra

2018

Int J Numerical Modelling

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This paper attempts to propose a new device as workfunction modulated dual metal rectangular recessed channel silicon on insulator (WMDMRRC-SOI) MOSFET. This model takes the advantage of recessed channel to reduce the hot-carrier effect and a linear variation of workfunction at source side metal gate to achieve improved threshold voltage and electron transportation efficiency. The characteristics of WMDMRRC-SOI MOSFET are analyzed in terms of electron behaviour like mobility, temperature, and velocity in the channel region. The impact of negative junction depth on threshold voltage and short-channel effects like drain induced barrier lowering, subthreshold slope are analyzed to optimize the characteristics of the proposed architecture.Performance parameters of WMDMRRC-SOI MOSFET are compared with the results of DMRRC-SOI MOSFET and conventional RRC-SOI MOSFET.The comparison interprets that with higher intrinsic gain and lower distortion, the proposed architecture gives better analog performance and enhanced short channel parameters. The results obtained are validated through Sentaurus TCAD device simulator. KEYWORDSnegative junction depth (NJD), recessed channel (RC), short-channel effects, silicon-on-insulator (SOI) | INTRODUCTIONScaling of MOS dimensions is essential in order to realize a high-speed and higher-packing density MOS integrated circuit, which results in high power consumption. Attempts to reduce power consumption lead to the degradation of MOSFET carrier transport efficiency. With aggressive technology scaling, the improvement in device reliability has been the prime focus in scaled MOSFET. Thus, performance enhancement can be achieved by overcoming the undesirable short-channel effects. [1][2][3] These barriers can be overcome by silicon-on-insulator (SOI) technology, which is implemented by assimilating an oxide layer on silicon body giving a perfect isolation to avoid latch up in conventional MOS structure. MOSFET along with SOI technology is popular for high temperature applications, as it provides lower leakage current at source/drain junction. Due to its better radiation tolerance, it is also useful for space applications. Above all, the steeper subthreshold characteristics make this device suitable for faster switching circuit applications. Although SOI technology is widely used, still some problems like gate transport inefficiency persists. 4-11

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