Effect of stacking chips and inlet positions on void formation in the encapsulation of 3D stacked flip-chip package

Optimization of pin through hole connector in thermal fluid–structure interaction analysis of wave soldering process using response surface methodology

“…Thus, this study focuses on the filling process and the fluid mechanism. The motion of molten solder in the simulation is described by using 3D incompressible transport equations, namely, continuity equation, Navier-Stokes equation, and conservation of energy, and written as [19].…”

Analysis of encapsulation process in 3D stacked chips with different microbump array

“…A transparent mold assembly [11] was fabricated for the experiment. The experiment was set up accordingly as shown in Fig.…”

“…Kamal curing model was applied for modeling the EMC curing rate. Many scholars [9][10][11][12][16][17][18] have used these viscosity and curing models in predicting the encapsulation process of electronic packaging. The equations of Kamal curing model can be expressed as…”

“…This defect is closely related to mold design, EMC material selection and process optimization. Khor et al [11] studied on the encapsulation process in 3D stacked flip chip packaging. In their numerical study, the increasing number of stacked flip chips caused increasingly serious air entrapment defect.…”

Active Infrared Thermography for Visualizing Subsurface Micro Voids in an Epoxy Molding Compound

“…In reality, epoxies are hydrophilic so that it can absorb moisture when exposed to a humid environment [3]. One of the most typical defects in the EMC is a micro void caused by swelled moisture between the EMC and staked-chip scale package [4]. This type of defect so called subsurface micro void can expand according to varying external and internal temperature of EMC with inducing unnecessary stresses to the EMC.…”