Effect of surface free energy in gate dielectric in pentacene thin-film transistors

Abstract

The surface free energy of a dielectric has a strong influence on the performance of pentacene thin-film transistors. Research shows that by matching surface free energy in the interface of the dielectric and the orthorhombic thin-film phase of pentacene film, the field-effect mobility of transistors is enhanced reaching above 2.0cm2∕Vs. The authors suggested that a more complete first monolayer of pentacene was formed upon the gate dielectric surface with almost identical surface free energy, benefiting carrier transportation. The research also discusses the mechanism of surface free energy effects on the crystalline size and structural disorder in pentacene film.

Interfacial Heterogeneity of Surface Energy in Organic Field‐Effect Transistors

“…[16][17][18][19][20][21][22][23] Wu has suggested [ 37 ] that the variation in surface energy as a function of MW stems from the different surface energies of chain ends and repeat units (see Equation 1 and Equation 2). The chain ends of PS have been reported to have a lower surface energy than the repeat units (e.g., the surface energy of the -CH-(phenyl ring edge) is reported as about 45.1 mN m − 1, and the -CH 3 is of 23.0-30.5 mN m − 1 ).…”

“…[16][17][18] In previous literature, the surface energy is usually calculated by measurements of contact angles at different points on the surface. [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23] However contact angle measurements is a 'statistic-average' method that can only indicate differences at a millimeter level, and obviously cannot describe whether or not the interfacial state is homogeneous on the nanometer scale. [16][17][18][19][20][21][22][23] The latter is crucial, because the surface energy of the dielectric mainly infl uences the performances of OFETs at the interface on just such a nanometer scale.…”

Growth related properties of pentacene thin film transistors with different gate dielectrics

“…The use of high-k dielectrics alone enables a large lowering of operating voltage [25][26][27] but also induce polarization effect which lead to carrier self trapping and consequently to electrical instabilities and mobility degradation [22,28]. Several papers reported combination of high-k inorganic and low-k polymeric dielectric either in form of composite layer [29,30] or as polymer/high-k bilayer [21,22,[31][32][33]. This allows to process low operating voltage device and in the mean time to get rid of polarization induced transport degradation.…”

A Solution-Processed Air-Stable Perylene Diimide Derivative for N-type Organic Thin Film Transistors

“…[14,15,17] However, indepth studies and analyses are needed to further clarify the detailed mechanisms.…”

“…[13] The surface energy matching between TC-PDI-F (36 mJ m À2 ) and LPD-SiO 2 (35 mJ m À2 ) could favor TC-PDI-F film adhesion and formation. [14][15][16] As the growth rate of LPD-SiO 2 depends on the growth temperature, we optimized the growth temperature at 40 8C and time for 8 hr to obtain smoother LPD-SiO 2 films. The thickness of LPD-SiO 2 is about 200 nm as confirmed by cross-sectional scanning electron microscopy (SEM).…”