2014 International Conference on Informatics, Electronics &Amp; Vision (ICIEV) 2014
DOI: 10.1109/iciev.2014.6850689
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Effect of technology scaling on leakage power consumption in on-chip switches

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“…โ€ข ๐‘ƒ ๐‘ ๐‘ก๐‘Ž๐‘ก๐‘–๐‘ is the static power Apparently in the CMOS, it is observed that when the capacitance is reduced by 30%, the power dissipation is reduced by 50%; similarly the 30% reduction of voltage leads to the 50% further reduction of the power. Static power is the constant use of force on the Gates due to the receding position from the source to the ground, except for the position of the Gates and the switch function [28]. The static power (Pstatic) scattered on the router and links can be stated as:…”
Section: Power Estimationmentioning
confidence: 99%
“…โ€ข ๐‘ƒ ๐‘ ๐‘ก๐‘Ž๐‘ก๐‘–๐‘ is the static power Apparently in the CMOS, it is observed that when the capacitance is reduced by 30%, the power dissipation is reduced by 50%; similarly the 30% reduction of voltage leads to the 50% further reduction of the power. Static power is the constant use of force on the Gates due to the receding position from the source to the ground, except for the position of the Gates and the switch function [28]. The static power (Pstatic) scattered on the router and links can be stated as:…”
Section: Power Estimationmentioning
confidence: 99%