Effect of Temperature on 16 nm n-FiNFET

Abstract

This research presents the effect of temperature that influence to the performance of 16 nm SOI n-FinFET structure. The structure has created with structure tool on GTS Framework. The transistor has 1 nanometer HfO2 gate oxide with all metal contact and biased on Minimos-NT tool, with variation of temperatures from 300 K to 420 K with 30 K per step. The result found the decrease in saturation current, threshold voltage and mobility. The temperature brought electron and rose the density of electron as the potential from power supply that energized to the structure. They made mobility fall with them rising. The temperature makes a performance of FinFET structure.

High Temperature Effects on the Static Performance of 14 nm TG SOI N FinFET

“…The higher performance ratio for this simulation is 2.4  10 8  10 6 which shows that the device operation is good at T  77 K [3][4][5][6][7][8][9].…”

“…The electrons in the valence band of the n-type drain will tunnel through the thinned band gap into the conduction band, and they will be collected at the drain contact and form part of the drain current, whereas the remaining holes will be collected at the source contact and will contribute to the source leakage current [8][9][10][11][12][13].…”

“…Fig. 8-Ratio ION / IOFF performance The decrease of the performance ION / IOFF ratio is linked to the increase of the tunneling currents (Band to Band Tunneling and Trap Assisted Tunneling).The tunneling current increase is due to the choice of the geometric parameters like oxide thickness which leads to the raising of the conduction band, so we have more leakage current between the gate and the channel.The higher performance ratio for this simulation is 2.4  10 8  10 6 which shows that the device operation is good at T  77 K[3][4][5][6][7][8][9].…”