Effect of the Hybrid Etching Methods on the Field Emission Characteristics of Mo-Tip Field Emitter Arrays

Abstract

Field emission display (FED) is a promising flat panel display (FPD), which provides a superior brightness, wide viewing angle, variety of colors, fast response time, and wide range of operating temperatures. Though some prototypes of FEDs are realized, 1,2 until now the success in its manufacturing depends on the fabrication technologies for uniform and stable field emitter arrays (FEAs), spacers with a high aspect ratio, and a low voltage phosphor.Most research on FEAs was focused on lowering the threshold voltage and increasing the emission current. 3,4 However, to improve the operating stability of FED, making FEAs with less gate leakage current is one of the most important issues. It is well known that the stability of FEAs depends on the geometrical shape both of the field emitter and the gate insulator. 5-9 Some simulation results 6 suggest that an emission current increases with the edge slope of the insulator, and the maximum electric field is obtained when the insulator edge lies at the same level with the gate edge. In the case that a vertical shape of gate insulator can be formed by dry etching, which has higher electric field on the tip apex and the gate insulator, so, the dry-type FEAs in which the insulator edge lies at the same level with the gate edge can have higher emission current and higher gate leakage currents. In this case, to decrease the gate leakage current of drytype FEAs while the emission current increases, several processes with different etching steps have been used. 10,11 This work begins by considering that the etched shape of gate insulator can be one of the most important parameters for improving the emission stability of the FEAs. Based on this assumption, we carried out a new etching process for Mo-FEAs called a hybrid etching method to optimize the shape of the gate insulator. Electron emission currents were measured for the two kinds of FEAs corresponding to each etching method and the electric field distribution on the tip apex and gate insulator were simulated for the two kinds of single triode using a simulation tool of SNU-FEAT 6 which is discussed.Experimental As a first step, the electric field on the apex of a tip and a gate insulator for an emitter were simulated by using an This program is based on finite element method (FEM) analysis, and includes the routines of automatic mesh generation and device analysis. Next, two kinds of Spindt-type Mo-tip FEAs were fabricated on a heavily doped n-type silicon wafer, FEAs with a drytype gate-insulator by dry etching, and FEAs with a hybrid-type gateinsulator by hybrid etching. The fabrication process for all FEAs in this work is fundamentally the same as that reported by Spindt et al. 12 Thermal oxide of 1.1 and 0.25 m thick sputtered Cr layers were deposited sequentially on heavily doped n-type Si wafer, and after the defining of 1.5 m diam holes by photolithography, the gate metal layer was etched by reactive ion etching (RIE) with a mixture of 50% O 2 and 50% Cl 2 at the rf power of 150 W. Then the gate insulator was op...

Characterizations of Ag-catalyzed ZnO nanostructures prepared by vapor–solid mechanism

“…FEDs use less power consumption than plasma display panels (PDP) and liquid crystal displays (LCD). A FED usually comprises a cathode plane (field emitter array, FEA) at the rear, a narrow vacuum gap in the middle, and an anode plane (phosphor screen) that forms the faceplate on which the image is formed [1,2]. The FEA configuration is arguably the most complicated structure in the FED, where electron conducting tracks are first arranged on a substrate.…”