Effect of the process flow on negative-bias-temperature-instability

Scarpa, A.; Marwijk, L. van; Cacciato, A.; Ballarin, Francesco

doi:10.1109/ppid.2003.1200943

Cited by 7 publications

(2 citation statements)

References 8 publications

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“…Gate-oxide damage during plasma processes has been widely investigated and is known as plasma process-induced damage (PPID). PPID has been reported to degrade device long-term reliability such as time-dependent dielectric breakdown [3] and negative bias temperature instability (NBTI) [4].…”

Section: Introductionmentioning

confidence: 99%

Threshold Voltage Shift Due to Mechanical Stress-Enhanced Plasma Process-Induced Damage in 0.13-$\mu\hbox{m}$ pMOSFET

Kong

Tao

et al. 2007

IEEE Electron Device Lett.

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Mechanical stress-enhanced plasma process-induced damage (PPID) in 0.13-µm pMOSFET was investigated. The PPID, which was initially charged neutral, became positively charged during hydrogen annealing, thus, changing the PMOS threshold voltage (V th ). Different device structures were designed to evaluate the mechanical stress effects on PPID. The features of these positive charges, including the PPID induced V th shift, and its channel length dependence were also investigated.Index Terms-Hydrogen anneal, mechanical stress, plasma process-induced damage (PPID), positive oxide charge, threshold voltage shift.

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Section: Introductionmentioning

confidence: 99%

Threshold Voltage Shift Due to Mechanical Stress-Enhanced Plasma Process-Induced Damage in 0.13-$\mu\hbox{m}$ pMOSFET

Kong

Tao

et al. 2007

IEEE Electron Device Lett.

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“…Indeed, boron penetration has been observed by Yamamoto et al [37] to enhance positive oxide charge generation but to suppress interface trap generation. Reduced interface trap generation is attributed to formation of Si-F bonds from BF 2 boron implant [37], [67]. Enhanced positive oxide charge has been attributed to increased oxide defects due to boron in the oxides.…”

Section: Hydrogen-mentioning

confidence: 99%

Experimental and theoretical studies of negative bias temperature instability in ultra-thin gate dielectrics

Tan¹

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This thesis is a collection of my research work at the Nanyang Technological University, as well as the dedicated guidance, encouragement, and support from A/Prof. Chen Tu Pei, who has served as my research advisor during the entire course of research. Without his investment of time and energy this research would never reach the fruition. I also deeply appreciate Dr. Lap Chan from Chartered Semiconductor Manufacturing for his guidance, suggestions and support throughout my research at NTU and Chartered. I am further indebted to Dr. Ang Chew Hoe for his continuous technical support during all these years. I would like to thank Soon Jiamei, who generously shared her expertise and knowledge in first-principles modeling with me. The award of a research scholarship by the NTU and A-Star is also gratefully acknowledged. Some of my fondest memories at Chartered are of my fellowship with those graduate students in the Special Project group. They have brought insight, intelligence, entertainment, and friendship, which have made my life at, Chartered an unforgettable one. Finally, I would like to express my deeply gratitude to my family especially my parent (Tan Yu long and Yau Chau Hwai) for their love, care, understanding, support and encouragement during all these years. Lastly, I thank my wife, Wendy Lee, without her patience, continuous support and strong belief, all these things would have never been possible.

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Robustness of nanometer CMOS designs: signal integrity, variability and reliability

Veendrick¹

2008

Nanometer CMOS ICs

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Effect of the process flow on negative-bias-temperature-instability

Cited by 7 publications

References 8 publications

Threshold Voltage Shift Due to Mechanical Stress-Enhanced Plasma Process-Induced Damage in 0.13-$\mu\hbox{m}$ pMOSFET

Threshold Voltage Shift Due to Mechanical Stress-Enhanced Plasma Process-Induced Damage in 0.13-$\mu\hbox{m}$ pMOSFET

Experimental and theoretical studies of negative bias temperature instability in ultra-thin gate dielectrics

Robustness of nanometer CMOS designs: signal integrity, variability and reliability

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