Effect of Thermal Mechanical Behaviors of Cu on Stress Distribution in Cu-Filled Through-Silicon Vias Under Heat Treatment

Zhao, Xu; Ma, Limin; Wang, Yishu; Guo, Fu

doi:10.1007/s11664-017-5885-y

Cited by 7 publications

(1 citation statement)

References 18 publications

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“…The key challenge associated with the long-term structural reliability of TSV technology stems are the different thermal expansion coefficients (CTEs) of Cu (17.5 × 10 −6 K −1 ) and Si (2.6 × 10 −6 K −1 ), which can lead to thermal stresses in these structures during thermal excursion of microelectronic devices [7,47]. The presence of large thermal stresses in TSV structures can be particularly detrimental to silicon, which is a brittle material.…”

Section: (4) Tsv Conductancementioning

confidence: 99%

A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis

Wang

Duan

et al. 2023

Applied Sciences

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This review investigates the measurement methods employed to assess the geometry and electrical properties of through-silicon vias (TSVs) and examines the reliability issues associated with TSVs in 3D integrated circuits (ICs). Presently, measurements of TSVs primarily focus on their geometry, filling defects, and the integrity of the insulating dielectric liner. Non-destructive measurement techniques for TSV contours and copper fillings have emerged as a significant area of research. This review discusses the non-destructive measurement of contours using high-frequency signal analysis methods, which aid in determining the stress distribution and reliability risks of TSVs. Additionally, a non-destructive thermal detection method is presented for identifying copper fillings in TSVs. This method exploits the distinct external characteristics exhibited by intact and defective TSVs under thermoelectric coupling excitation. The reliability risks associated with TSVs in service primarily arise from copper contamination, thermal fields in 3D-ICs, stress fields, noise coupling between TSVs, and the interactions among multiple physical fields. These reliability risks impose stringent requirements on the design of 3D-ICs featuring TSVs. It is necessary to electrically characterize the influence of copper contamination resulting from the TSV filling process on the reliability of 3D-ICs over time. Furthermore, the assessment of stress distribution in TSVs necessitates a combination of micro-Raman spectroscopy and finite element simulations. To mitigate cross-coupling effects between TSVs, the insertion of a shield between them is proposed. For efficient optimization of shield placement at the chip level, the geometric model of TSV cross-coupling requires continuous refinement for finite element calculations. Numerical simulations based on finite element methods, artificial intelligence, and machine learning have been applied in this field. Nonetheless, comprehensive design tools and methods in this domain are still lacking. Moreover, the increasing integration of 3D-ICs poses challenges to the manufacturing process of TSVs.

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Section: (4) Tsv Conductancementioning

confidence: 99%