Effect of thin film interference on process latitude in deep ultraviolet lithography

Abstract

Articles you may be interested inThree-dimensional electron-beam lithography using an all-dry resist process A heavy ion implanted pocket 0.10 μm n-type metal-oxide-semiconductor field effect transistor with hybrid lithography (electron-beam/deep ultraviolet) and specific gate passivation process Silicon metal-oxide-semiconductor field-effect transistor with gate structures defined by scanned probe lithography J. FIG. 2. Simulation result of normalized absorption of illumination light in resist as a function of resist thickness ͑NAϭ0.5 and ϭ0.6͒. FIG. 3. CD variations ͑space widths͒ of ͑a͒ line/spaceϭ250/300 nm patterns ͑550 nm pitch͒ at dose/focusϭ19 mJ/cm 2 /0.1 m and ͑b͒ line/spaceϭ375/450 nm patterns ͑825 nm pitch͒ at dose/focusϭ17 mJ/cm 2 /Ϫ0.2 m as a function of resist thickness. 2929 Azuma, Sato, and Aochi: Effect of thin film interference 2929 JVST B -Microelectronics and Nanometer Structures Redistribution subject to AVS license or copyright; see http://scitation.aip.org/termsconditions. Download

Application of a thin-resist process for KrF imaging to 130 nm device fabrication

“…[1][2][3] The resist process, which uses extremely thin resist down to 80 nm in thickness, has also been introduced for 130 nm KrF lithography. [1][2][3] The resist process, which uses extremely thin resist down to 80 nm in thickness, has also been introduced for 130 nm KrF lithography.…”

Fabrication of Sub-10 nm Metal Wire Circuits using Directed Self-Assembly of Block Copolymers

“…The electrical process level-test element group (PL-TEG) yield could reveal the process viability from the perspective of totally practical performance for semiconductor device manufacturing including critical dimension (CD) control, defect control, pattern placement error, space width roughness (SWR), space edge roughness (SER), and process windows in pattern transfer process [6,11,12]. guide patterns were exposed on a spin-on-glass (SOG), spin-on-carbon (SOC), SiO 2 , amorphous silicon (a-Si), SiO 2 stacked silicon substrate on a 1.3 numerical aperture (NA) ArF excimer laser immersion scanner (NSR S610C, Nikon Corp.) The SiO 2 guide patterns were then fabricated using the resist patterns on the SOG and the SOC [13][14][15][16] on a dry etcher (Tactras SCCM-T4, Tokyo Electron Ltd.). A random BCP solution as a neutral layer was then grafted and a high χ lamellar BCP solution with 20 nm L 0 (domain spacing) was applied on the SiO 2 guide patterns using a Clean Track ACT12 (Tokyo Electron Ltd.).…”