TELKOMNIKA
 2015
DOI: 10.12928/telkomnika.v13i2.1298
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Effect of Underlap and its Soft Error Performance in 30 nm Junctionless-based 6T-SRAM Cell

Chitra Pandy
1
,
Ramakrishnan V. Narayanan
2

Abstract: As CMOS device is scaling down significantly, the sensitivity of Integrated Circuits (ICs)

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