Effective cache replacement policy for packet processing cache

Abstract

SummaryOwing to the explosive increase in Internet traffic, increasing the throughput and energy efficiency of core routers is an important issue for future internet. Accessing the ternary content addressable memory (TCAM) in a core router can significantly degrade its throughput and energy efficiency owing to its low operating frequency and power consuming operations. To improve the throughput and energy‐efficiency of core routers, packet processing caches (PPCs) can be potentially used. PPCs can reduce the number of TCAM accesses by storing the TCAM lookup results in a fast and low‐energy cache memory and reusing them to process subsequent packets. To enhance the PPC performance, it is important to reduce the number of PPC misses. However, the PPC miss rate of the state‐of‐the‐art PPC is still high owing to its small capacity. In this study, we propose an effective cache replacement policy, called elevator cache (ELC) to improve the PPC miss rate. Our simulation results showed that the 8‐way ELC, which can be implementable at low hardware cost, reduced the number of PPC misses by 17.1% and 5.67% in comparison to the 4‐way least recently used (LRU) and the 4‐way ELC, respectively. Consequently, it was found that the 8‐way ELC can achieve a 1.21 times higher throughput (560 Gbps) while consuming 83% energy in comparison to conventional PPCs.

Estimating the Memory Consumption of a Hardware IP Defragmentation Block

“…IP defragmentation has more similarities to the TCP reassembly than to connection tracking since both require buffering and maintenance of the state. Tracking the state of L4 connections is optional, and implementations based on the concept of a cache (e.g., Yamaki [14], Tanaka [15] in Table 2) often do not keep the connection state. The bandwidth criterion in Table 1 means the availability of the relevant traffic in network samples.…”

“…The advent of high-bandwidth fiber networks revived the interest in the energy efficiency of TCAM memory, which led Tanaka [15] to propose a flow cache as a means of reducing the TCAM hit rate. The general evaluation of flow cache memory performance is presented in Czekaj and Jamro [32], and subsequently, in Yamaki [14]. A recent example of using an FPGA-based Smart NIC for a flow-aware network processing can be found in Li [33].…”

“…An obvious research direction when it comes to IP defragmentation is a replacement policy employed be the flow table. Some research mentioned in Section 2 (e.g., Yamaki [14]) was exclusively focused on developing a technique that can beat the LRU either in performance or resource efficiency. Since the problem of IP defragmentation is somewhat different from connection tracking (as discussed in Section 1.3), it deserves an independent assessment of cache replacement policies.…”

“…The size of the flow table A × B (point 1) was chosen to be relatively small, which is typical for the network accelerators based on SRAM memory (e.g., Intel X700 [11]). Other hardware-oriented publications (e.g., Yamaki [14]) also consider the size in the order of a thousand entries.…”

Leveraging Replacement Algorithm for Improved Cache Management System

“…Because of the re issue of the computer science area and monologist of the hardware architecture and the system software system of the branch based central processing design locates the anatomy of the computer based aided system which is called the new cache memory management system [2]. The real time amplification and mission of the system software of the data system and the management system of the computer science [3]. The system of the cache memory approach is the associatively of the data base management system [4].…”